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    WIRING PATTERN FORMING METHOD, DEVICE AND ELECTRONIC APPARATUS
    143.
    发明申请
    WIRING PATTERN FORMING METHOD, DEVICE AND ELECTRONIC APPARATUS 审中-公开
    布线图案形成方法，装置和电子装置

    公开(公告)号：US20080121412A1

    公开(公告)日：2008-05-29

    申请号：US11946098

    申请日：2007-11-28

    Applicant: Jun YAMADA ,  Junichiro SHINOZAKI

    Inventor： Jun YAMADA ,  Junichiro SHINOZAKI

    IPC: H05K1/00 ,  B05D5/12

    CPC classification number: H05K3/125 ,  H05K2201/09272 ,  H05K2201/0939 ,  H05K2203/013

    Abstract: A wiring pattern forming method comprises: relatively moving a droplet discharging head and a substrate, each in a predetermined direction; discharging a liquid material in a form of droplet onto the substrate from a plurality of discharging nozzles formed on the droplet discharging head; forming a predetermined wiring pattern on the substrate; and forming an end portion of a wiring pattern in a tapered shape, or a bent portion of a wiring pattern in a curved shape.

    Abstract translation: 一种布线图案形成方法，包括：在预定方向上相对移动液滴喷射头和基底; 从形成在液滴喷射头上的多个排出喷嘴将液滴形式的液体材料排放到基板上; 在所述基板上形成预定的布线图案; 并且形成呈锥形的布线图案的端部或弯曲形状的布线图案的弯曲部分。

    Printed circuit board having arrays of lands arranged inside and outside of each other having a reduced terminal-pitch
    144.
    发明授权
    Printed circuit board having arrays of lands arranged inside and outside of each other having a reduced terminal-pitch 失效
    具有布置在彼此内部和外部的具有减小的端子间距的平台阵列的印刷电路板

    公开(公告)号：US06218630B1

    公开(公告)日：2001-04-17

    申请号：US09107478

    申请日：1998-06-30

    Applicant: Kotaro Takigami

    Inventor： Kotaro Takigami

    IPC: H01R1204

    CPC classification number: H05K1/111 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09227 ,  H05K2201/0939 ,  H05K2201/094 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611

    Abstract: A printed circuit board includes a plurality of lands thereon. The size D2 of the outer land 3 in the direction along the outside array is less than the size D1 of the inner land 1 in the direction along the inside array. Therefore, it is possible to pass the pattern 4 with enough clearance against the outer land 3. The outer lands 3 are formed with an oval, elliptical or oblong shape. Namely, the size D3 of the outer land 3 in the direction perpendicular to the direction of the outside array is greater than the size D2. Then, it is possible to ensure a sufficient reliability of a soldered part. Preferably, the connected area 5 between the inner land 1 and the pattern 4 and the connected area 7 between the outer land 3 and the pattern 6 are formed as a shape of a tear-drop. Then, the patterns 4, 6 cannot be easily cut by a thermal stock or a heat cycle. The solder resist 8 is coated, around the outer land 3, from an outer area to an inner area of the outer land 3, except for the central area 3A. The resist 8 is further coated, around the inner land 1, from an outer area to an inner area of the inner land 1, except for the central area 1A. Then, each area 5, 7 is reinforced by the resist 8. Further, since a clearance between exposed areas 1A and a clearance between exposed areas 3A are widened, a bridge of solder does not easily occur.

    Abstract translation: 印刷电路板包括多个焊盘。 沿着外部阵列的方向的外部焊盘3的尺寸D2小于沿着内部阵列的方向的内部焊盘1的尺寸D1。 因此，可以使图案4以足够的间隙通过外缘3。外缘3形成为椭圆形，椭圆形或椭圆形。 也就是说，在与外部阵列的方向垂直的方向上的外部焊盘3的尺寸D3大于尺寸D2。 然后，可以确保焊接部件的足够的可靠性。 优选地，内部平台1和图案4之间的连接区域5和外部凸台3与图案6之间的连接区域7形成为泪滴形状。 然后，图案4,6不能容易地被热料或热循环切断。 除了中心区域3A之外，阻焊剂8围绕外部焊盘3从外部区域外围区域涂覆到外部区域3的内部区域。 除了中心区域1A之外，抗蚀剂8从内部区域1的外部区域到内部区域1的内部区域进一步被涂覆在内部区域1周围。 然后，每个区域5,7由抗蚀剂8加强。此外，由于暴露区域1A之间的间隙和暴露区域3A之间的间隙变宽，所以焊接桥不容易发生。

    Heat transfer apparatus suitable for use in a circuit board assembly
    146.
    发明授权
    Heat transfer apparatus suitable for use in a circuit board assembly 失效
    适用于电路板组件的传热装置

    公开(公告)号：US5831826A

    公开(公告)日：1998-11-03

    申请号：US717055

    申请日：1996-09-20

    Applicant: James Edward Van Ryswyk

    Inventor： James Edward Van Ryswyk

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/32 ,  H05K3/34 ,  H05K7/20

    CPC classification number: H05K7/20445 ,  H05K1/0206 ,  H05K1/11 ,  H05K2201/0373 ,  H05K2201/066 ,  H05K2201/0939 ,  H05K2201/09663 ,  H05K2203/043 ,  H05K3/0061 ,  H05K3/325 ,  H05K3/3468

    Abstract: A heat transfer apparatus is carried on a substrate (204) having top and bottom surfaces (212, 214). The heat transfer apparatus includes a pad (220/222), at least one via (224/226), and a plurality of pads (302). The pad (220/222) is carried on the top surface (212) of the substrate (204) to electrically connect to an electronic component (228/230). The via (224/226) intersects the pad (220/222) and extends between the top and bottom surfaces (212, 214) of the substrate (204). The plurality of pads (302) are carried on the bottom surface (214) of the substrate (204) beneath the pad (220/222). The via (224/226) intersects one of the plurality of pads (302) to transfer heat generated during operation of the electronic component (228/230) thereto.

    Abstract translation: 传热装置承载在具有顶表面和底表面（212,214）的基底（204）上。 传热装置包括垫（220/222），至少一个通孔（224/226）和多个垫（302）。 衬垫（220/222）被承载在衬底（204）的顶表面（212）上以电连接到电子部件（228/230）。 通孔（224/226）与焊盘（220/222）相交并且在衬底（204）的顶表面和底表面（212,214）之间延伸。 多个焊盘（302）被承载在衬垫（220/222）下方的衬底（204）的底表面（214）上。 通孔（224/226）与多个焊盘（302）中的一个相交，以将电子部件（228/230）的操作期间产生的热传递到其上。

    Method and apparatus for aligning and attaching a surface mount component
    147.
    发明授权
    Method and apparatus for aligning and attaching a surface mount component 失效
    用于对准和附接表面安装部件的方法和装置

    公开(公告)号：US5311405A

    公开(公告)日：1994-05-10

    申请号：US100834

    申请日：1993-08-02

    Applicant: David A. Tribbey ,  Henry F. Liebman ,  Allen D. Hertz ,  Peter E. Albertson

    Inventor： David A. Tribbey ,  Henry F. Liebman ,  Allen D. Hertz ,  Peter E. Albertson

    IPC: B23K1/00 ,  H05K1/11 ,  H05K3/34 ,  H05K13/04 ,  H05K7/10

    CPC classification number: H05K1/111 ,  B23K1/0016 ,  H05K13/0465 ,  H05K3/3442 ,  B23K2201/36 ,  H05K2201/0939 ,  H05K2201/0989 ,  H05K2201/10636 ,  H05K2203/048 ,  H05K2203/0545 ,  Y02P70/611 ,  Y02P70/613

    Abstract: A method and an apparatus align and attach a leadless surface mount component (402) including a termination at each end of the component (402). The termination has bottom (704) and end (702) portions for attaching to a corresponding pad on a substrate (102) by a reflow solder process (1200). A pad arrangement (100) is formed including two opposite pads (108), each pad (108) occupying a tri-oval-shaped area. The tri-oval-shaped area includes an elliptical area (110) substantially centered under the bottom portion (704) of the corresponding termination of the component (402) when the component (402) is aligned with the pad arrangement (100), and an arcuate area (112) contiguous with the elliptical area (110) and extending towards the opposite pad (108) in a central lengthwise direction. A solder paste (202) is applied to the elliptical area (110), and thereafter reflowed, whereby solder (302) in the solder paste (202) liquefies and flows onto the arcuate area (112), thereby facilitating alignment of the component (402) with the pad arrangement (100).

    Abstract translation: 一种方法和装置将包括在组件（402）的每个端部处的端接件的无引线表面安装部件（402）对准和附接。 终端具有底部（704）和端部（702）部分，用于通过回流焊接工艺（1200）附接到衬底（102）上的对应衬垫。 形成包括两个相对的焊盘（108）的焊盘装置（100），每个焊盘（108）占据三椭圆形的区域。 当所述部件（402）与所述垫装置（100）对准时，所述三椭圆形区域包括基本上位于所述部件（402）的相应终端的底部（704）下方的中心的椭圆形区域（110），以及 与椭圆形区域（110）相邻并在中心纵向方向上朝向相对的垫（108）延伸的弧形区域（112）。 将焊膏（202）施加到椭圆形区域（110）上，然后回流焊接，由此焊膏（202）中的焊料（302）液化并流到弧形区域（112），从而有助于部件 402）。

    ELECTRONIC SYSTEM
    150.
    发明公开
    ELECTRONIC SYSTEM 审中-公开

    公开(公告)号：US20240314920A1

    公开(公告)日：2024-09-19

    申请号：US18595907

    申请日：2024-03-05

    Applicant: MEDIATEK INC.

    Inventor： Tso-Ju YI ,  Chung-Fa LEE

    IPC: H05K1/02 ,  H05K1/11

    CPC classification number: H05K1/0206 ,  H05K1/0222 ,  H05K1/114 ,  H05K2201/0939 ,  H05K2201/09509 ,  H05K2201/10734

    Abstract: An electronic system is provided. The electronic system includes a base and a semiconductor device. The base having a device-attach region includes a build-up layer structure, a vertical interconnect structure and a first through via. The vertical interconnect structure and the first through via are formed passing through the build-up layer structure and located in the device-attach region. The vertical interconnect structure includes a buried via and a blind via electrically coupled to the buried via. The first through via is a straight through via. The semiconductor device is mounted on the device-attach region of the base.

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