公开(公告)号：KR1020140058919A

公开(公告)日：2014-05-15

申请号：KR1020120125386

申请日：2012-11-07

Applicant: 삼성전기주식회사

Inventor： 박승욱 ,  이동환 ,  김진구 ,  이창배 ,  크리스틴로메로

IPC: H05K3/46 ,  H05K9/00

CPC classification number: H05K1/0216 ,  H05K3/4602 ,  H05K3/4673 ,  H05K2201/0281 ,  H05K2201/0323 ,  H05K2201/0723 ,  H05K2201/09581 ,  Y10T29/49165

Abstract: The present invention relates to a printed circuit board and a method for manufacturing the same. Disclosed are the printed circuit board for a thinner and densified board, which comprises: a core layer having a first circuit line layer on one side or both sides; an insulation layer laminated on one side or both sides of the core layer by one or more layer; and a second circuit line layer formed on one side of the insulation layer, but comprising a conductive core inside the upper and lower parts of the insulation layer joined to the second circuit line layer requiring an electromagnetic shield, or comprising a conductive core inside the insulation layer inside the core layer joined to the first circuit line layer requiring an electromagnetic shield, and a method for manufacturing the same.

Abstract translation: 印刷电路板及其制造方法技术领域本发明涉及印刷电路板及其制造方法。 公开了一种用于更薄和更致密化的板的印刷电路板，其包括：芯层，其一侧或两侧具有第一电路线层; 通过一层或多层层压在芯层的一侧或两侧的绝缘层; 以及形成在所述绝缘层的一侧上的第二电路线层，但是在所述绝缘层的上部和下部中包含导体芯，所述导电芯与所述第二电路线层接合，需要电磁屏蔽，或者在所述绝缘层内部包括导电芯 连接到需要电磁屏蔽的第一电路线层的芯层内的层及其制造方法。

公开(公告)号：KR1020090037795A

公开(公告)日：2009-04-16

申请号：KR1020080077434

申请日：2008-08-07

Applicant: 후지쯔 가부시끼가이샤

Inventor： 마에하라야스모토 ,  이이다겐지 ,  아베도모유키 ,  히라노신 ,  나카가와다카시 ,  요시무라히데아키 ,  야마와키세이고 ,  오자키노리카즈

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/427 ,  H05K1/115 ,  H05K1/116 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4691 ,  H05K2201/0347 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09809 ,  H05K2203/1178 ,  H05K2203/135 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate is provided to improve adhesion between the substrate and a wiring layer by etching a conductive layer formed in a surface of the substrate with a predetermined pattern. A penetration hole(18) is formed in a substrate(16). A penetration hole is a pilot hole. A plated through hole is passed through the plated through hole. The plating is performed in the substrate. An inner wall of the penetration hole is coated with a plating layer(19). A photoresist is laminated in the surface of the substrate. The photoresist is exposed and developed. A resist pattern(72) is formed. The resist pattern covers at least planar region of the penetration hole. A conductive layer is formed in the surface of the substrate and is etched. The conductive layer is etched. The resist pattern is used as a mask. The substrate includes a conductive core unit(10).

Abstract translation: 提供一种用于制造衬底的方法，以通过以预定图案蚀刻形成在衬底的表面中的导电层来改善衬底和布线层之间的粘合性。 在基板（16）上形成贯通孔（18）。 穿孔是导孔。 电镀通孔穿过电镀通孔。 在基板上进行电镀。 穿孔的内壁涂有镀层（19）。 光致抗蚀剂层叠在基板的表面上。 光致抗蚀剂被曝光和显影。 形成抗蚀剂图案（72）。 抗蚀剂图案覆盖贯通孔的至少平面区域。 在衬底的表面形成导电层并进行蚀刻。 导电层被蚀刻。 抗蚀剂图案用作掩模。 基板包括导电芯单元（10）。

公开(公告)号：KR1020060051037A

公开(公告)日：2006-05-19

申请号：KR1020050082537

申请日：2005-09-06

Applicant: 세이코 엡슨 가부시키가이샤

Inventor： 신타테츠요시 ,  사쿠라다가즈아키 ,  야마다준

IPC: H05K3/46 ,  H05K3/10 ,  B82Y30/00

CPC classification number: H05K3/4664 ,  H01L51/0004 ,  H05K3/125 ,  H05K2201/09581 ,  H05K2201/09909 ,  H05K2203/013 ,  H05K2203/1173 ,  H05K2203/1476

Abstract: 본 발명은 액적 토출 장치를 이용하여 비어 홀을 구비한 다층 구조를 형성하는 것을 과제로 한다.
다층 구조 형성 방법이 도전성 재료의 액적을 토출하여 물체 표면 위에 도전성 재료 패턴을 형성하는 스텝과, 상기 도전성 재료 패턴을 소성하여 배선 패턴을 형성하는 스텝과, 광경화성 재료를 포함하는 제 1 절연 재료의 액적을 토출하여, 상기 배선 패턴 위에서 비어 홀의 가장자리를 두르는 제 1 절연 재료 패턴을 형성하는 스텝과, 상기 제 1 절연 재료 패턴을 경화하여 비어 홀의 가장자리를 두르는 제 1 절연 패턴을 형성하는 스텝과, 상기 물체 표면을 친액화하는 스텝과, 광경화성 재료를 포함하는 제 2 절연 재료의 액적을 토출하여 상기 배선 패턴과 친액화된 상기 물체 표면을 덮는 동시에, 상기 제 1 절연 패턴을 둘러싸는 제 2 절연 재료 패턴을 형성하는 스텝과, 상기 제 2 절연 재료 패턴을 경화하여 상기 제 1 절연 패턴을 둘러싸는 제 2 절연 패턴을 형성하는 스텝을 포함한다.
다층 구조 형성 방법, 액적 토출 장치, 절연 재료, 도전성 재료, 광경화성 재료, 배선 기판 제조 방법.

公开(公告)号：KR1019910009483B1

公开(公告)日：1991-11-16

申请号：KR1019890004719

申请日：1989-04-10

Applicant: 미쓰비시덴키 가부시키가이샤

Inventor： 마스이가쯔에 ,  고바야시이사오 ,  구보따시게루 ,  모리와끼도시모또

IPC: H05K3/46 ,  H05K3/06

CPC classification number: G03F7/168 ,  G03F7/161 ,  H05K3/0094 ,  H05K3/064 ,  H05K2201/09581 ,  H05K2203/092 ,  H05K2203/107 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: 내용 없음.

公开(公告)号：US09499912B2

公开(公告)日：2016-11-22

申请号：US14287075

申请日：2014-05-26

Applicant: Rohm and Haas Electronic Materials LLC

Inventor： Julia Kozhukh ,  Zuhra I. Niazimbetova ,  Kristen M. Milum

IPC: H05K3/42 ,  C23C18/31 ,  H05K3/18 ,  H05K1/03 ,  C09D183/14 ,  C09D183/08 ,  C08G77/388 ,  C08L83/08 ,  G03F7/075 ,  C23C18/18

CPC classification number: C23C18/31 ,  C08G77/388 ,  C08L83/08 ,  C09D183/08 ,  C09D183/14 ,  C23C18/18 ,  G03F7/0751 ,  H05K1/03 ,  H05K3/181 ,  H05K3/422 ,  H05K3/427 ,  H05K2201/09581

Abstract: Copolymers of diglycidyl ether terminated polysiloxane compounds and non-aromatic polyamines are used in the preparation of dielectric materials for electroless metal plating. The copolymers may be used in the manufacture of printed circuit boards such as in cleaning and conditioning through-holes prior to electroless metallization.

Abstract translation: 二缩水甘油醚封端的聚硅氧烷化合物和非芳族多胺的共聚物用于无电镀金属电介质材料的制备。 共聚物可用于制造印刷电路板，例如在无电镀金属化之前的清洁和调节通孔中。

公开(公告)号：US20160336223A1

公开(公告)日：2016-11-17

申请号：US15220143

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Harold Ryan Chase ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Mark Hlad

IPC: H01L21/768 ,  H01L23/36 ,  H01L21/288

CPC classification number: H01L21/76879 ,  H01L21/288 ,  H01L21/76838 ,  H01L23/00 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H05K1/0219 ,  H05K1/0222 ,  H05K3/4602 ,  H05K2201/09581 ,  H01L2924/014

Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

公开(公告)号：US20150357699A1

公开(公告)日：2015-12-10

申请号：US14762440

申请日：2014-01-27

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Hiroyuki YAMAGUCHI ,  Hajime NAKAYAMA ,  Haruo OGINO ,  Seiichi KURIHARA

IPC: H01P5/08 ,  B23K26/36 ,  H01P11/00 ,  H01P3/08 ,  H01P3/06

CPC classification number: H01P5/085 ,  H01P3/06 ,  H01P3/08 ,  H01P11/003 ,  H01P11/005 ,  H05K1/0237 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09581 ,  H05K2201/09809 ,  H05K2201/10287 ,  H05K2201/10356 ,  Y10T29/49167

Abstract: A multilayer wiring plate includes a coaxial wire includes a signal line, an insulation coating and an outer peripheral conductor. An insulating layer is arranged on an inner or outer layer side. A metal film circuit is arranged by the intermediary of the insulating layer, and the metal film circuit and the outer peripheral conductor and signal line of the coaxial wire are connected. A signal line connection part that connects the signal line to the metal film circuit includes a penetration hole A that passes through the insulating layer and the outer peripheral conductor; the coaxial wire from which the outer peripheral conductor is removed inside the penetration hole A; a hole filling resin filled inside the penetration hole A; a penetration hole B that passes through the hole filling resin and the signal line; and a plated layer arranged on an inner wall of the penetration hole B.

Abstract translation: 多层布线板包括同轴线，其包括信号线，绝缘涂层和外周导体。 绝缘层设置在内层或外层一侧。 金属膜电路通过绝缘层中间布置，金属膜电路和同轴线的外周导体和信号线连接。 将信号线连接到金属膜电路的信号线连接部分包括穿过绝缘层和外周导体的穿透孔A; 在穿透孔A内除去外周导体的同轴线; 填充在穿透孔A内的孔填充树脂; 穿过孔填充树脂和信号线的穿透孔B; 以及布置在穿透孔B的内壁上的镀层。

公开(公告)号：US20150230342A1

公开(公告)日：2015-08-13

申请号：US14244299

申请日：2014-04-03

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H05K3/00 ,  H05K1/11 ,  H05K1/03

CPC classification number: H05K1/115 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/029 ,  H05K2201/09581 ,  Y10T29/49124 ,  H01L2924/00

Abstract: In some embodiments, a carrier substrate for an integrated circuit may include a core, a first plurality of openings, and a first insulating material. The core may include a first surface and a second surface substantially opposing the first surface. The first plurality of openings may extend from the first surface to the second surface of the core. In some embodiments, the first insulating material may be applied to a surface of the first plurality of openings. In some embodiments, the first plurality of openings may include a first conductor extending through each of the first plurality of openings from the first surface to the second surface. In some embodiments, at least a first subset of the first plurality of openings may include a first charge and at least a second subset of the first plurality of openings may include a second charge. The first charge and the second charge may be different.

Abstract translation: 在一些实施例中，用于集成电路的载体衬底可以包括芯，第一多个开口和第一绝缘材料。 芯可以包括基本上与第一表面相对的第一表面和第二表面。 第一多个开口可以从芯的第一表面延伸到第二表面。 在一些实施例中，第一绝缘材料可以施加到第一多个开口的表面。 在一些实施例中，第一多个开口可以包括延伸穿过第一多个开口中的每一个从第一表面到第二表面的第一导体。 在一些实施例中，第一多个开口的至少第一子集可以包括第一电荷，并且第一多个开口的至少第二子集可以包括第二电荷。 第一次充电和第二次充电可能不同。

公开(公告)号：US08872334B2

公开(公告)日：2014-10-28

申请号：US13636324

申请日：2011-03-22

Applicant: Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori

Inventor： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori

IPC: H01L23/48 ,  H01L23/538 ,  H05K3/46 ,  H05K1/18 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498

CPC classification number: H05K1/185 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/18 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/4605 ,  H05K2201/09581 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2924/00

Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.

Abstract translation: 在包括多个布线层和绝缘层的多层布线结构中的包含半导体元件的半导体器件的制造方法中，将半导体元件安装在硅支撑体上，该硅支撑体的厚度减小到期望的厚度并且配备有 多个穿过厚度方向的通孔; 形成绝缘层以嵌入半导体元件; 那么在与硅半导体元件相连的硅支撑体的相对表面上形成多个布线层。 因此，可以减少在制造中在半导体元件附近发生的翘曲，从而改善整个半导体器件的翘曲轮廓。 此外，可以防止半导体元件变得无用，提高成品率，并且可以生产具有高密度封装性能的薄型半导体器件。

公开(公告)号：US08704101B2

公开(公告)日：2014-04-22

申请号：US13539505

申请日：2012-07-02

Applicant: Shih-Hao Sun

Inventor： Shih-Hao Sun

IPC: H05K1/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/3677 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5389 ,  H01L25/16 ,  H01L25/167 ,  H01L33/64 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2924/181 ,  H05K1/0204 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09581 ,  H05K2201/10416 ,  H05K2203/1469 ,  Y10T29/49139 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In a manufacturing method of a package carrier, a substrate having an upper surface, a lower surface, and an opening communicating the two surfaces is provided. An electronic device is disposed inside the opening. A first insulation layer and a superimposed first metal layer are laminated on the upper surface; a second insulation layer and a superimposed second metal layer are laminated on the lower surface. The opening is filled with the first and second insulation layers. First blind holes, second blind holes, and a heat-dissipation channel are formed. A third metal layer is formed on the first and second blind holes and an inner wall of the heat-dissipation channel. A heat-conducting device is disposed inside the heat-dissipation channel and fixed into the heat-dissipation channel via an insulation material. The first and second metal layers are patterned to form a first patterned metal layer and a second patterned metal layer.

Abstract translation: 在包装载体的制造方法中，提供具有上表面，下表面和连通两个表面的开口的基板。 电子设备设置在开口内。 第一绝缘层和叠置的第一金属层层叠在上表面上; 第二绝缘层和叠加的第二金属层层叠在下表面上。 开口填充有第一和第二绝缘层。 形成第一盲孔，第二盲孔和散热通道。 在第一和第二盲孔和散热通道的内壁上形成第三金属层。 导热装置设置在散热通道的内部并通过绝缘材料固定到散热通道中。 图案化第一和第二金属层以形成第一图案化金属层和第二图案化金属层。