公开(公告)号：JP2002042481A

公开(公告)日：2002-02-08

申请号：JP2001196763

申请日：2001-06-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To provide a row constituting of spare memory cells which is realized more simply and more effectively in a memory circuit, and to provide a circuit in which the occupied surface area is smaller than a conventional circuit having spare cells. SOLUTION: This dynamic memory circuit includes memory cells arranged in rows and columns, each row which can be started by a word line, each column fomed by cells connected to first and second bit lines, at least one spare row formed by static memory cells being coped so as to be started to replace a memory cell row, and each spare cell connected to the first and the second bit lines of a column of a circuit.

公开(公告)号：JP2001266364A

公开(公告)日：2001-09-28

申请号：JP2001045919

申请日：2001-02-22

Applicant: ST MICROELECTRONICS SA

Inventor： GRAFFOULIERE PHILIPPE

IPC: G11B21/08 ,  G11B7/085 ,  G11B7/09

Abstract: PROBLEM TO BE SOLVED: To provide the method for controlling the positioning of a light beam incident on a track of an optical disk. SOLUTION: The beam reflected by the disk is detected by using an optical pickup furnished with a photodetector, and basic signals A, B, C, D are respectively outputted from the photodetector. The positioning error of the beam with respect to the track is obtained from the basic signal. To be more specific, two sampled secondary signals (A+C, B+D) are produced from the basic signals, and the time difference between them represents the positioning error of the beam with respect to the track. A continuous latest value of the time difference (T) between them is obtained by a sampling frequency in such a manner that a maximum value MAX of a continuous latest correlation function between two sampled secondary signals is searched.

公开(公告)号：JP2001256116A

公开(公告)日：2001-09-21

申请号：JP2000382738

申请日：2000-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F12/14 ,  G06F1/00 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/34

Abstract: PROBLEM TO BE SOLVED: To safely transfer data in a programmable circuit (CP) provided with at least one control unit (UC), a read-only memory(ROM1) provided with transfer data, a writable memory(RAM1) and a data bus(DBUS) connected between the read-only memory(ROM1) and the writable memory (RAM1). SOLUTION: The secret data element of N-bytes to be transferred is shifted by a byte unit on the data bus(DBUS), the respective bytes are shifted on the data bus(DBUS) at least once and the bytes are shifted in a different order for each transfer of the same data element. When a loading indicator (ZR) takes a prescribed value (IN), the transfer of the secret data element is completed.

公开(公告)号：JP2001189935A

公开(公告)日：2001-07-10

申请号：JP2000335824

申请日：2000-11-02

Applicant: ST MICROELECTRONICS SA

Inventor： MOUTIN JEAN MICHEL ,  MARTY PIERRE

IPC: G06F12/00 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  H04N7/24

Abstract: PROBLEM TO BE SOLVED: To properly provide a priority of a common memory, when an MPEG decoder and microcomputer use the common memory. SOLUTION: The MPEG decoder includes a microprocessor, decoder that decodes an image sequence, memory in common use with the microprocessor and the decoder, circuit that evaluates a delay in the decoder, and control circuit that gives memory access priority to the decoder, when the delay in the decoder is higher than a prescribed level or gives the memory access priority to the microprocessor when it is not.

公开(公告)号：JP2001185715A

公开(公告)日：2001-07-06

申请号：JP2000332258

申请日：2000-10-31

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  CORNIBERT LAURENT

IPC: H01L29/74 ,  H01L21/225 ,  H01L21/331 ,  H01L21/332 ,  H01L21/76 ,  H01L21/761 ,  H01L21/763 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a vertical power element in which the thickness of layer that determines the breakdown voltage of the element is optimized. SOLUTION: In a method of manufacturing the vertical power element on a silicon wafer, a second-conductivity lightly-doped epitaxial layer having such a thickness that can withstand the maximum voltage impressed upon the power element during operation is formed on the upper surface of a first-conductivity heavily-doped substrate and at least one area corresponding to the power element is divided by insulating walls in the wafer. The insulating walls are formed by forming trenches by etching the epitaxial layer and diffusing a first- conductivity dopant having a high doping level into the wafer from the trenches.

公开(公告)号：JP2001136107A

公开(公告)日：2001-05-18

申请号：JP2000261126

申请日：2000-08-30

Applicant: ST MICROELECTRONICS SA

Inventor： PRAT GILDAS ,  CHIANALE ALAIN

IPC: H01F19/00 ,  H03H11/32 ,  H04B1/58 ,  H04B3/03 ,  H04B3/20 ,  H04M1/76

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetrical transformer for telephone line that prevents a structure of an echo cancellation circuit provided between a transformer and a transmission/reception head from being complicated by increasing a voltage in a transmission direction without decreasing a voltage in a receiving direction. SOLUTION: The asymmetrical transformer is provided between a 2-wire line and a transceiver, has at least one primary winding with 1st number of turns connected to the 2-wire line and at least three secondary windings of series connection connected to the transceiver. The asymmetrical transformer is characterized by that respective number of turns of the secondary windings connected in series depends on a desired transformation ratio for the transmission and reception.

公开(公告)号：JP2001118394A

公开(公告)日：2001-04-27

申请号：JP2000281033

申请日：2000-09-14

Applicant: ST MICROELECTRONICS SA

Inventor： NAURA DAVID ,  ZINK SEBASTIEN ,  BERTRAND BERTRAND

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/10

Abstract: PROBLEM TO BE SOLVED: To decrease the number of required high voltage latch without lengthening excessively a page mode access time. SOLUTION: In a page mode write-in method of a non-volatile memory being electrically erasable and programmable in an integrated circuit, a written page corresponds to a column of a memory array. This method comprises write-in of information elements for selecting a page written in a storage latch combined with columns of a non-volatile memory array, an initial stage including writing each data written in a page in a temporary storage device, and a write-in stage selecting a row of a non-volatile memory array conforming to contents of the temporary storage device. The page mode write-in means is provided with one latch per one column of a non-volatile memory array, and a control logic circuit outputting a row selecting signal in accordance with contents of the temporary storage device at a stage at which a column of the non-volatile memory array is written, in order to storing page selection information elements.

公开(公告)号：JP2001024160A

公开(公告)日：2001-01-26

申请号：JP2000175207

申请日：2000-06-12

Applicant: ST MICROELECTRONICS SA

Inventor： BERTHIOT DENIS

IPC: H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H03H7/06

Abstract: PROBLEM TO BE SOLVED: To enable a protective filtering circuit to acquire both a protective function against overcharging and a filtering function, by respectively connecting one main area to the other areas with portions of a reverse conductivity area to a reduced surface. SOLUTION: Metallization M11 is formed on the rear surface side of a P-type substrate 30 and metallization M12, M13, and M14 which are in contact with a diffusion area 31 are formed on the front surface side of the substrate 30. The diffusion area 31 contains portions 31-1 and 31-2 which are not covered with the metallization, are respectively extended between the area covered with the metallization M14 and the areas covered with the metallizations M12 and M13, and connect the metallization M14 of a main area to the metallization M12 and M13.

公开(公告)号：JP2001016548A

公开(公告)日：2001-01-19

申请号：JP2000151121

申请日：2000-05-23

Applicant: ST MICROELECTRONICS SA

Inventor： VAN DEN BOSSCHE NADIA

IPC: H04N5/85 ,  H04L9/36 ,  H04N5/783 ,  H04N5/91 ,  H04N5/92 ,  H04N7/26 ,  H04N9/804 ,  H04N7/24

Abstract: PROBLEM TO BE SOLVED: To provide a circuit which deciphers and decodes two discontinuous searched picture collected from the sequence of an enciphered picture, prevents a deciphered picture from being copied and avoids remarkable increase of the processing quantity of a microprocessor. SOLUTION: The circuit for decoding first and second discontinuous searched pictures to be acquired from the sequence of encoded pictures partitioned by a picture starting cord includes a processor 5 which divides the sequence into plural ciphered data packets, selects the data packet including data on the searched picture and marks the head of the last enciphered data packet including data on a first searched picture, and a filtering circuit 11 which deletes deciphered data following the picture start code in the data packet having a mark header, deletes deciphered data preceding the picture start code in the next selected data/packet and is arranged on the output side of the deciphering device 7.

公开(公告)号：JP2000347854A

公开(公告)日：2000-12-15

申请号：JP2000135053

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  WOJCIESZAK LAURENT ,  BOUVIER STEPHANE

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a decoding device which is simple and good in power efficiency and supplies a decoding output to an execution device accurately according to an instruction mode of a computer. SOLUTION: The decoding device 20 is equipped with 1st and 2nd decoders 50 and 52, and 54 and 56 which are so connected as to receive bit arrays of 1st and 2nd specific lengths. The 1st and 2nd decoders operate in parallel so as to generate respective outputs. Switches MUX6 and MUX7 select one of the outputs according to an instruction mode of a processor. The instruction mode of this processor affects the length of the bit array which needs to actually be decoded.