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公开(公告)号：KR100550519B1
公开(公告)日：2006-02-10
申请号：KR1020040107867
申请日：2004-12-17
Applicant: 한국전자통신연구원
IPC: H01L21/336
Abstract: 본 발명은 반도체 소자의 제조방법에 관한 것으로, 스트레인드 실리콘 채널층과 도핑된 SiGe층이 적층되어 형성된 SOI 기판을 이용하여 SiGe와 스트레인드 실리콘 간의 높은 식각선택비를 이용하여 상대적으로 용이하게 완전공핍평 채널소자를 제조할 수 있을 뿐만 아니라, 접합저항과 용량의 감소를 비교적 단순한 공정으로 가능하게 하는 소오스/드레인 공정과, 고성능 소자에 필수적인 금속 게이트의 적용과 게이트 폭의 축소가 용이한 반도체 소자의 제조 방법을 제공한다.
반도체 소자, 스트레인드 실리콘, SOI, SiGe, MOSAbstract translation: 本发明涉及一种制造半导体器件的方法，并且更具体地涉及一种制造半导体器件的方法，该半导体器件使用通过堆叠应变硅沟道层和掺杂SiGe层而形成的SOI衬底， 通过相对简单的工艺可以减小结电阻和电容的源极/漏极工艺以及可以应用于高性能器件所需的金属栅极的耗尽型沟道器件和半导体器件的制造， 及其制造方法。
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公开(公告)号：KR1020050112471A
公开(公告)日：2005-11-30
申请号：KR1020040037571
申请日：2004-05-25
Applicant: 한국전자통신연구원
IPC: H01L21/336
CPC classification number: H01L29/785 , H01L29/66818
Abstract: 본 발명은 다중 게이트 모스 트랜지스터 및 그의 제조 방법에 관한 것으로, 단결정 실리콘 패턴의 형태와 실리콘의 결정 방향에 따른 열산화 속도 차이를 이용하여 유선(∩) 형태의 채널, 점차 증가하는 형태의 확장 영역 및 상승된 구조의 소스 및 드레인을 구현한다. 채널이 유선(∩) 형태로 형성됨으로써 전계의 집중으로 인한 소자의 신뢰성 저하가 방지되며, 채널의 상부와 양 측벽이 게이트 전극으로 둘러싸여지기 때문에 게이트 전압에 의한 전류 구동 능력이 우수해진다. 또한, 크기가 증가된 확장 영역으로 인해 전류 밀집 현상이 방지되며, 상승된 소스 드레인 구조에 의해 소스 및 드레인 직렬 저항이 감소되어 전류 구동 능력이 증대된다.
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公开(公告)号：KR1020050054600A
公开(公告)日：2005-06-10
申请号：KR1020030087991
申请日：2003-12-05
Applicant: 한국전자통신연구원
IPC: G06F17/50
CPC classification number: H04L67/025
Abstract: 재구성형 SoC(System On a Chip) 구현시, 목적시스템 내부에서 재구성에만 사용되는 메모리의 공간을 없애고 이를 별도의 서버에 설치해 둔 뒤 재구성의 필요에 따라 구성용 데이터를 인터넷(유선 혹은 무선)을 통해 불러와 SoC의 내외부에 있는 메모리를 구성용으로 사용하게 하는 것을 그 특징으로 한다. 아울러 SoC 내외부의 메모리에 있는 데이터 중 재구성 후에도 보존되어야 할 데이터를 서버에 이전하여, 비워진 SoC 내외부의 메모리를 구성용 메모리로 사용 후 보존되어야 할 데이터를 복원시키는 방법을 제안한다.
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公开(公告)号：KR100440445B1
公开(公告)日：2004-07-15
申请号：KR1020010060460
申请日：2001-09-28
Applicant: 한국전자통신연구원
IPC: H01F27/245
Abstract: PURPOSE: A coaxial inductor is provided to make it possible to change the size and shape of an inductor by forming a magnetic substance and a conductor having a common axis, and to prevent the influence of noise caused by the exposure of an inductor by coating the inductor with an electromagnetic wave shielding film. CONSTITUTION: A thin insulating film(22) is coated on a conductor(21). A core magnetic substance(23), selected from Fe, nickel, cobalt, NiFe, chrome, molybdenum, tungsten silicon steel, ferrite or an alloy thereof, is coated in a thickness of hundreds of Å to tens of mm on the insulating film(22). An electromagnetic wave shielding film(24) is formed on the core magnetic substance(23). Finally, an insulating film(25) is coated on the electromagnetic wave shielding film(24) to form a coaxial inductor(20). The conductor(21), insulating film(22), magnetic substance(23), electromagnetic wave shielding film(24) and insulating film(25) have a common axis.
Abstract translation: 目的：提供一种同轴电感器，通过形成具有共同轴线的磁性物质和导体，可以改变电感器的尺寸和形状，并且可以防止由于电感器的暴露而引起的噪声的影响 带电磁波屏蔽膜的电感器。 构成：在导体（21）上涂覆薄绝缘膜（22）。 选自Fe，镍，钴，NiFe，铬，钼，钨硅钢，铁素体或它们的合金的核心磁性物质（23）被涂覆成数百埃耳的厚度; 到绝缘膜（22）上的数十毫米。 电磁波屏蔽膜（24）形成在核磁性物质（23）上。 最后，在电磁波屏蔽膜（24）上涂敷绝缘膜（25），形成同轴电感器（20）。 导体（21），绝缘膜（22），磁性体（23），电磁波屏蔽膜（24）和绝缘膜（25）具有共同的轴。
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公开(公告)号：KR1020040051365A
公开(公告)日：2004-06-18
申请号：KR1020020079286
申请日：2002-12-12
Applicant: 한국전자통신연구원
IPC: H03G3/30
CPC classification number: H03G1/0023 , H03F3/4508
Abstract: PURPOSE: A variable gain amplifier is provided to supply a variable amplification function for the input signal has a wide range by the external control signal at a low supply power. CONSTITUTION: A variable gain amplifier includes an input signal application and variable gain control circuit(110) and a current/voltage converting circuit. The input signal application and variable gain control circuit(110) receives a first and a second input signal from the differential input terminal. The input signal application and variable gain control circuit(110) amplifies the first and the second differential signals by amplifying the difference between the first and the second input signals. The input signal application and variable gain control circuit(110) outputs the differential signal of the variable voltage gain in response to the gain voltage control voltage signal. The current/voltage converting circuit receives the first and the second differential signals outputted from the input signal application and variable gain control circuit(110) and outputs the signals by converting the first and the second differential signal into the first and the second output voltages in response to the first and the second bias voltages.
Abstract translation: 目的：提供可变增益放大器，为输入信号提供可变放大功能，通过外部控制信号以较低的电源供电，具有较宽的范围。 构成：可变增益放大器包括输入信号应用和可变增益控制电路（110）和电流/电压转换电路。 输入信号应用和可变增益控制电路（110）从差分输入端接收第一和第二输入信号。 输入信号应用和可变增益控制电路（110）通过放大第一和第二输入信号之间的差来放大第一和第二差分信号。 输入信号应用和可变增益控制电路（110）响应于增益电压控制电压信号输出可变电压增益的差分信号。 电流/电压转换电路接收从输入信号应用和可变增益控制电路（110）输出的第一和第二差分信号，并将第一和第二差分信号转换成第一和第二输出电压 响应于第一和第二偏置电压。
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Patent Agency Ranking
公开(公告)号：KR1020040050591A
公开(公告)日：2004-06-16
申请号：KR1020020078448
申请日：2002-12-10
Applicant: 한국전자통신연구원
IPC: H03G3/30
Abstract: PURPOSE: A variable gain amplifier is provided which operates at a low supply voltage with low power consumption characteristics. CONSTITUTION: An input part(110) is formed in a differential type, and outputs the first and the second differential signal by amplifying a difference between the first and the second input signal according to the first bias voltage. A variable gain controller(120) receives the first and the second differential signal, and outputs the first and the second variable current by varying the amplitude of the first and the second differential signal according to the first and the second gain control voltage signal. And a current-voltage converter(130) receives the first and the second variable current, and converts the first and the second variable current into the first and the second output voltage according to the second and the third bias voltage.
Abstract translation: 目的：提供可变增益放大器，工作在低电源电压和低功耗特性。 构成：输入部分（110）形成为差分类型，并且通过根据第一偏置电压放大第一和第二输入信号之间的差来输出第一和第二差分信号。 可变增益控制器（120）接收第一和第二差分信号，并且通过根据第一和第二增益控制电压信号改变第一和第二差分信号的幅度来输出第一和第二可变电流。 并且电流 - 电压转换器（130）接收第一和第二可变电流，并且根据第二和第三偏置电压将第一和第二可变电流转换成第一和第二输出电压。
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公开(公告)号：KR1020040048603A
公开(公告)日：2004-06-10
申请号：KR1020020076521
申请日：2002-12-04
Applicant: 한국전자통신연구원
IPC: H04J11/00
CPC classification number: H04L27/265 , H04L27/2657 , H04L27/2662 , H04L2027/0026
Abstract: PURPOSE: An OFDM(Orthogonal Frequency Division Multiplexing) receiver is provided to simplify a structure and reduce a manufacturing cost by using only one FFT/IFFT unit. CONSTITUTION: An OFDM receiver includes a multiplexer, an FFT/IFFT unit, a synchronization circuit, and a symbol demodulator. The multiplexer(450) is used for outputting selectively the first signal of a transmission data frame signal and the second signal according to the first control signal. The FFT/IFFT unit(460) performs an FFT process for the first signal or performs an IFFT process for the second signal according to the second control signal. The synchronization circuit(470) inputs the first and the second signals into the multiplexer, inputs the second control signal into the FFT/IFFT unit, and receives an output signal of the FFT/IFFT unit. The symbol demodulator(480) is used for demodulating the output signal of the FFT/IFFT and outputting final data.
Abstract translation: 目的：提供OFDM（正交频分复用）接收机，通过仅使用一个FFT / IFFT单元来简化结构并降低制造成本。 构成：OFDM接收机包括多路复用器，FFT / IFFT单元，同步电路和符号解调器。 复用器（450）用于根据第一控制信号有选择地输出发送数据帧信号的第一信号和第二信号。 FFT / IFFT单元（460）对第一信号执行FFT处理，或者根据第二控制信号对第二信号执行IFFT处理。 同步电路（470）将第一和第二信号输入多路复用器，将第二控制信号输入到FFT / IFFT单元中，并接收FFT / IFFT单元的输出信号。 符号解调器（480）用于对FFT / IFFT的输出信号进行解调并输出最终数据。
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公开(公告)号：KR1020040046477A
公开(公告)日：2004-06-05
申请号：KR1020020074418
申请日：2002-11-27
Applicant: 한국전자통신연구원
IPC: G11C29/00
Abstract: PURPOSE: A system on chip(SoC) test circuit and its test method are provided to test an internal flip flop and a memory and an IP of a SoC with a data pattern inputted and being output directly. CONSTITUTION: According to the SoC test circuit to test an internal circuit(110) and a flip flop and a memory(200) and an IP of a SoC, an input data generation unit(120) inputs an output signal of the internal circuit or scan data input to the memory and the internal circuit according to a scan signal by receiving an output signal from the internal circuit and a scan signal and scan data from the external. And an output data generation part outputs a number of output data by selecting an output of the memory and an output of the IP and an output of the input data generation unit respectively according to a strobe input and the first and the second selection input.
Abstract translation: 目的：提供片上系统（SoC）测试电路及其测试方法，用于测试内部触发器，存储器和SoC的IP，并输入数据模式并直接输出。 构成：根据用于测试内部电路（110）和触发器以及存储器（200）和SoC的IP的SoC测试电路，输入数据生成单元（120）输入内部电路的输出信号或 根据扫描信号，通过接收来自内部电路的输出信号和扫描信号以及从外部扫描数据来扫描输入到存储器和内部电路的数据。 并且输出数据生成部分根据选通输入和第一和第二选择输入分别选择存储器的输出和IP的输出以及输入数据生成单元的输出来输出多个输出数据。
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公开(公告)号：KR1020040045513A
公开(公告)日：2004-06-02
申请号：KR1020020073314
申请日：2002-11-23
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A PDP and a method for manufacturing the PDP are provided to achieve a low voltage and low power operation by lowering a plasma generating voltage and improve an effective cell efficiency and discharge response speed. CONSTITUTION: A plasma display panel comprises a first substrate, a second substrate(800), a barrier rib(700), a phosphor layer(850), an electron gun(900), and a discharge electrode. The second substrate is spaced apart from the first substrate and provides a space for discharge gas. The barrier rib defines cells between the first substrate and the second substrate. The phosphor layer is formed on the second substrate. The electron gun is formed on the first substrate and discharges the electrons for discharging the gas. The discharge electrode is formed on the rear surface of the first substrate and applies AC voltage for discharging.
Abstract translation: 目的：提供PDP和制造PDP的方法，通过降低等离子体产生电压并提高有效的电池效率和放电响应速度来实现低电压和低功率操作。 构成：等离子体显示面板包括第一基板，第二基板（800），隔壁（700），荧光体层（850），电子枪（900）和放电电极。 第二基板与第一基板间隔开并提供放电气体的空间。 隔壁限定了第一基板和第二基板之间的单元。 磷光体层形成在第二基板上。 电子枪形成在第一衬底上并排出用于排出气体的电子。 放电电极形成在第一基板的后表面上并施加用于放电的AC电压。
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公开(公告)号：KR1020040043279A
公开(公告)日：2004-05-24
申请号：KR1020020071498
申请日：2002-11-18
Applicant: 한국전자통신연구원
CPC classification number: H01L29/66621 , H01L21/2255 , H01L29/66553 , H01L29/7834
Abstract: PURPOSE: A short channel MOS(Metal Oxide Semiconductor) transistor and a manufacturing method thereof are provided to be capable of obtaining a nano-meter level channel region. CONSTITUTION: A MOS transistor is provided with a semiconductor substrate(1), an STI(Shallow Trench Isolation) region(19) formed at both sides of the semiconductor substrate, a source/drain region connected with the lateral portion of the STI region, and a plurality of spacers(43) spaced apart from each other for contacting each source/drain region. The MOS transistor further includes a polysilicon layer(42) filled between the spacers for being used as a gate electrode, a gate isolating layer(41) for enclosing the lower portion of the polysilicon layer, and a source/drain expansion region(48) connected with the neighboring source/drain region. At this time, the length of the polysilicon layer is controlled by controlling the interval between spacers.
Abstract translation: 目的：提供一种短沟道MOS（金属氧化物半导体）晶体管及其制造方法，以能够获得纳米级信道区域。 构成：MOS晶体管设置有半导体基板（1），形成在半导体基板的两侧的STI（浅沟槽隔离）区域，与STI区域的横向部分连接的源极/漏极区域， 以及彼此间隔开的用于接触每个源极/漏极区域的多个间隔物（43）。 MOS晶体管还包括填充在用于栅电极的间隔物之间的多晶硅层（42），用于封闭多晶硅层的下部的栅极隔离层（41）和源极/漏极扩展区域（48） 与相邻的源/漏区连接。 此时，通过控制间隔物之间的间隔来控制多晶硅层的长度。
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