公开(公告)号：EP0164392A1

公开(公告)日：1985-12-18

申请号：EP85900239.0

申请日：1984-12-05

Applicant: DAHLBERG, Rolf ,  DAHLBERG, Tomas

Inventor： DAHLBERG, Rolf ,  DAHLBERG, Tomas

IPC: H05K1 ,  H05K3 ,  H05K7

CPC classification number: H05K1/0203 ,  H05K1/053 ,  H05K3/0061 ,  H05K3/28 ,  H05K3/386 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10303 ,  H05K2201/10553 ,  H05K2201/10689 ,  H05K2203/0315

Abstract: Carte de circuit imprimé possédant un élément de base de support (2) en aluminium anodisé. Un film de colle (4) est placé entre l'élément de base de support et une couche laminée (7) comportant un circuit imprimé (6a, 6b), le film de colle bouchant tous les pores dans le film anodique de l'élément de base de support.

公开(公告)号：KR1020130105546A

公开(公告)日：2013-09-25

申请号：KR1020130028189

申请日：2013-03-15

Applicant: 후지쯔 가부시끼가이샤

Inventor： 요시무라히데아키

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K1/115 ,  G01R31/2889 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/4038 ,  H05K3/425 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: PURPOSE: A manufacturing method of a wiring board and a passage structure are provided to reduce thermal stress by including a plurality of penetration through holes. CONSTITUTION: An external penetration hole passes through a core material. Insulation resin is filled in the external penetration hole. A first conductive layer (10A) is formed on the surface of the insulation resin. A land (10B) is formed around the first conductive layer. A wiring layer (20) is laminated on the core material.

Abstract translation: 目的：提供一种布线板和通道结构的制造方法，通过包括多个穿透孔来减少热应力。 构成：外部穿透孔穿过核心材料。 绝缘树脂填充在外部穿透孔中。 在绝缘树脂的表面上形成第一导电层（10A）。 在第一导电层周围形成焊盘（10B）。 布线层（20）层叠在芯材上。

公开(公告)号：KR100711334B1

公开(公告)日：2007-04-27

申请号：KR1020047021131

申请日：2003-06-27

Applicant: 피피지 인더스트리즈 오하이오 인코포레이티드

Inventor： 왕알란이 ,  올슨케빈씨 ,  디스테파노토마스에이치

IPC: H05K1/05 ,  H05K3/44

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: 본 발명에 따른 회로 기판층(2)은 절연 최상부층(10)과 절연 최하부층(14) 사이에 샌드위치된 전도성 시트(4)를 포함한다. 최상부 및 최하부층(10,14)과 전도성 시트(4)는 전도성 시트(4)의 에지(20)를 포함하는 에지를 가진 회로 기판층(2)을 정의한다. 절연 에지층(18)은 전도성 시트(4)의 모든 에지(20)를 상당히 도포한다.

公开(公告)号：KR100637819B1

公开(公告)日：2006-10-26

申请号：KR1020040107501

申请日：2004-12-17

Applicant: 산요덴키가부시키가이샤 ,  간또 산요 세미컨덕터즈 가부시끼가이샤

Inventor： 가나꾸보마사루

IPC: H05K1/05

CPC classification number: H01L23/4334 ,  H01L21/486 ,  H01L21/565 ,  H01L23/5384 ,  H01L23/564 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/4046 ,  H05K3/44 ,  H05K2201/09554 ,  H05K2201/10287 ,  H05K2203/0207 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20754 ,  H01L2924/2076 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: Disclosed are a hybrid integrated circuit device and a method of manufacturing thereof which can enhance reliability of connections between conductive patterns and a circuit board. A method of manufacturing the hybrid integrated circuit device comprises the steps of providing an insulating layer on a surface of the circuit board made of metal, forming conductive patterns on the surface of the insulating layer so as to constitute a plurality of units, forming exposure holes so as to penetrate the insulating layer in the respective units and thereby to expose the circuit board from bottom portions of the exposure holes, forming flat portions at the bottom portions of the exposure holes in the respective units, electrically connecting circuit elements to the conductive patterns in the respective units, electrically connecting the flat portions to the conductive patterns in the respective units by use of thin metallic wires, and separating the respective units.

公开(公告)号：KR1020040106211A

公开(公告)日：2004-12-17

申请号：KR1020040019284

申请日：2004-03-22

Applicant: 산요덴키가부시키가이샤

Inventor： 스즈끼다께시 ,  오스미가즈시게 ,  이찌하시준이찌 ,  이이무라도시유끼 ,  쯔유끼신이찌

IPC: H05K1/02

CPC classification number: H01L24/49 ,  H01L23/4334 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4046 ,  H05K3/44 ,  H05K2201/09554 ,  H05K2201/09772 ,  H05K2201/10287 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: PURPOSE: A hybrid integrated circuit device is provided to prevent erroneous operation and noise of electric circuit, by connecting a conductive pattern connected to a ground potential, to a metal substrate in the vicinity of a semiconductor device operating at a high speed. CONSTITUTION: A hybrid integrated circuit device(10) comprises a metal substrate(11) having a surface on which an insulation layer(17) is formed; a conductive pattern(12) formed on a surface of the insulation layer; a semiconductor element(15A) bonded on the conductive pattern; and a connection portion(20) or electrically connecting the conductive pattern and the metal substrate in the vicinity of the semiconductor element.

Abstract translation: 目的：提供混合集成电路装置，通过将连接到接地电位的导电图案连接到在高速运行的半导体器件附近的金属基板上来防止电路的错误操作和噪声。 构成：混合集成电路装置（10）包括金属基板（11），其上形成有绝缘层（17）的表面; 形成在所述绝缘层的表面上的导电图案（12） 接合在所述导电图案上的半导体元件（15A） 以及连接部分（20）或者在半导体元件附近电连接导电图案和金属基板。

公开(公告)号：KR1020000023423A

公开(公告)日：2000-04-25

申请号：KR1019990041126

申请日：1999-09-22

Applicant: 닛뽕덴끼 가부시끼가이샤

Inventor： 히라사와고끼 ,  오노데루오

IPC: H01L23/12

CPC classification number: H01L23/5384 ,  H01L21/4857 ,  H01L23/49861 ,  H01L23/5383 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K1/056 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2201/10924 ,  H05K2203/0554 ,  H05K2203/0733 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: A multi-layered wire structure and a method for fabricating thereof are provided to improve the reliability of connection between a filling layer and a wire layer of a multi-layered wire structure, without a process such as polishing deteriorating the yield of a product. CONSTITUTION: A multi-layered wire structure includes a bottom wire layer(103a), an intermediate insulation layer, a filling layer(106,112), a top wire layer(109a) and a plated layer(113). The bottom wired layer is formed on a lead frame through an insulation layer. The intermediate insulation layer is formed on the bottom wire layer and has a via hole in a fixed region so as to reveal a top part of the bottom wire layer. The filling layer is made of a conductive material and the via hole fills with the conductive material. The top wire layer is formed on the intermediate insulation layer and has an opening unit on a top part of the region where the via hole is formed. The plated layer is formed on the top wire layer and is connected to the filling layer.

Abstract translation: 目的：提供多层导线结构及其制造方法，以提高多层导线结构的填充层和线层之间的连接的可靠性，而抛光等工艺不会降低产品的产量 。 构成：多层导线结构包括底线层（103a），中间绝缘层，填充层（106,112），顶层层（109a）和镀层（113）。 底部布线层通过绝缘层形成在引线框架上。 中间绝缘层形成在底部线层上，并且在固定区域中具有通孔，以露出底部线层的顶部。 填充层由导电材料制成，通孔填充导电材料。 顶层层形成在中间绝缘层上，并且在形成通孔的区域的顶部具有开口单元。 镀层形成在顶部线层上并与填充层连接。

公开(公告)号：WO2015104072A9

公开(公告)日：2015-10-08

申请号：PCT/EP2014071994

申请日：2014-10-14

Applicant: AUTO KABEL MAN GMBH ,  TAZARINE WACIM ,  BETSCHER SIMON ,  GRONWALD FRANK

Inventor： TAZARINE WACIM ,  BETSCHER SIMON ,  GRONWALD FRANK

IPC: H05K1/02 ,  H01L23/367 ,  H05K1/05 ,  H05K1/11 ,  H05K1/14

CPC classification number: H05K1/145 ,  C23C14/042 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/056 ,  H05K1/111 ,  H05K1/117 ,  H05K1/142 ,  H05K1/181 ,  H05K1/182 ,  H05K3/28 ,  H05K3/282 ,  H05K3/368 ,  H05K2201/09372 ,  H05K2201/09554 ,  H05K2201/10166 ,  H05K2201/10689 ,  H05K2203/1377 ,  H01L2924/00

Abstract: Disclosed is a circuit comprising a first printed circuit board (2a) and a second printed circuit board (2b). The first circuit board is provided with a metal supporting board (14) and an insulating layer (8) which electrically insulates the metal supporting board on a surface, the supporting board being without any insulating layer in at least one connection region (10a-10d). The supporting board is metal-coated (12) in the connection region, and a contact (30a) of a semiconductor (30) is electrically contacted on the metal coating of the connection region. The second circuit board is provided with a metal supporting board (2b), an insulator (16) that electrically insulates the metal supporting board (24) on a surface, and a conducting layer (18) that is applied to the insulator. The insulator and the conducting layer have a breakdown region (21) in at least one contact zone, and at least one metal contact pad (20) is arranged in the contact zone in such a way that the contact pad is peripherally disposed at a distance from the insulator and from the conducting layer. The circuit boards in the circuit are separated from one another by an air gap (28) and are mechanically interconnected by at least one power semiconductor device (30).

Abstract translation: 电路具有第一电路板（2a）和第二电路板（2b）中。 第一印刷电路板设置有一金属载体板（14）和所述电绝缘的绝缘层（8）的表面上的金属支撑板，其中所述支撑板在所述至少一个连接部分（10A-10D）从所述绝缘层的分类。 承载板是金属的涂布在连接区域（12）和在端子区域的金属涂层，半导体的接触（30A）（30）电接触。 第二电路板设置有金属载体板（2b）中，电绝缘的绝缘体（16）和沉积在所述绝缘体（18）上的导电层的表面上的金属载体板（24）。 绝缘体和导电层中的至少一个接触区域被穿孔（21）中的接触面积un为在支撑板的至少一个金属接触垫（20），被布置为使得周向间隔开的接触焊盘是绝缘体和导电层。 在电路中，该电路板由通过至少一个功率半导体（30）相互连接的空气间隙（28）和机械地间隔开。

公开(公告)号：WO2008000529A1

公开(公告)日：2008-01-03

申请号：PCT/EP2007/053539

申请日：2007-04-12

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  ARTMANN, Jens

Inventor： ARTMANN, Jens

IPC: B60R16/023 ,  H05K1/14 ,  F16H61/00

CPC classification number: B60R16/0239 ,  H05K1/0306 ,  H05K1/142 ,  H05K1/147 ,  H05K3/0061 ,  H05K3/4046 ,  H05K5/0052 ,  H05K5/0082 ,  H05K2201/09554 ,  H05K2203/049

Abstract: Eine Trägervorrichtung hat einen Metallträger (1), einen Keramik-Leiterträger (2), der auf dem Metallträger (1) angeordnet ist, und einen Flex-Folien-Leiterträger (4), der mittels einer Bondverbindung mit dem Keramik-Leiterträger (2) elektrisch leitend gekoppelt ist und der mittels eines elektrisch leitenden Koppelelements (12) mit dem Metallträger (1) über Formschluss und/oder Kraftschluss elektrisch leitend gekoppelt ist.

Abstract translation: 载体装置具有金属支架（1），陶瓷电路载体（2），其被布置在所述金属支架（1），和一个柔性膜印刷电路载体（4）通过粘结化合物的方式连接到陶瓷电路载体（2） 是导电的，并通过一个导电耦合元件（12）与金属支架（1）通过正配合和/或摩擦连接被电传导地耦合的耦合装置。

公开(公告)号：WO2006099811A1

公开(公告)日：2006-09-28

申请号：PCT/CN2006/000492

申请日：2006-03-24

Applicant: 华为技术有限公司 ,  金俊文 ,  王界平 ,  李松林 ,  习炳涛

Inventor： 金俊文 ,  王界平 ,  李松林 ,  习炳涛

IPC: H05K3/42

CPC classification number: H05K1/0243 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/42 ,  H05K3/44 ,  H05K2201/09554 ,  H05K2201/10166

Abstract: A circuit board, in particular, a high-power printed circuit board assembly with the function of heat emission used for radio frequency circuit. Also a manufacturing method thereof which is used to solve the problem of electrical connecting between a copper layer and a metal component when the metal component is bonded to the printed circuit board. The printed circuit board assembly in this invention comprises a printed circuit board covered by a copper layer and a metal component that is bonded to the printed circuit board. It further comprises electric conducting holes which are bored through the copper layer and the metal component, and metal films are plated on the surface of inner wall of the electric conducting holes so as to make it be electrically connected between the copper layer and the metal component. The said manufacturing method comprises: a) a printed circuit board and a metal component are pressed together with an adhesive material between them to form an assembly; b) the assembly is bored to form the electric conducting holes and the electric conducting holes are through the copper layer and the metal component; c) metal films are plated on the surface of inner wall of the electric conducting holes so as to make it be electrically connected between the copper layer and the metal component.

公开(公告)号：WO2006053206A1

公开(公告)日：2006-05-18

申请号：PCT/US2005/040907

申请日：2005-11-10

Applicant: PPG INDUSTRIES OHIO, INC.

Inventor： OLSON, Kevin, C. ,  WANG, Alan, E. ,  ELENIUS, Peter ,  GOODMAN, Thomas, W.

IPC: H05K3/46 ,  H05K3/44

CPC classification number: H05K3/002 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135

Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Abstract translation: 多层电路板的电路板或每个电路板包括涂覆有覆盖导电片的一个表面的绝缘顶层的导电片，覆盖导电片的另一表面的绝缘底层和覆盖 导电片的边缘。 绝缘中间层可以夹在多层电路板组件的一对相邻电路板之间。 无地通孔或通孔可以延伸通过一个或多个电路板，用于连接其相对表面上的电导体。