公开(公告)号：EP1942557A1

公开(公告)日：2008-07-09

申请号：EP07120978.7

申请日：2007-11-19

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Nair, Deepukumar M.

IPC: H01Q15/00 ,  H01P1/203

CPC classification number: H01Q15/0026 ,  H01P1/2005 ,  H01Q15/006 ,  H05K1/0216 ,  H05K2201/09309 ,  H05K2201/09609 ,  Y10T29/49016

Abstract: A high-frequency Electromagnetic Bandgap (EBG) device (70,90), and a method (100) for making the device are provided. The device (70,90) includes a first substrate (72) including multiple conducting vias (74) forming a periodic lattice. The vias (74) ofthe first substrate (72) extend from the lower surface ofthe first substrate (72) to the upper surface of the first substrate (72). The device (70,90) also includes a second substrate (76) having multiple conducting vias (78) forming a periodic lattice. The vias (78) ofthe second substrate (76) extend from the lower surface of the second substrate (76) to the upper surface of the second substrate (76). The second substrate (76) is positioned adjacent to, and overlapping, the first substrate (72), such that the lower surface of the second substrate (76) is in contact with the upper surface of the first substrate (72), and such that a plurality of vias (78) of the second substrate (76) are in contact with a corresponding plurality of vias (74) of the first substrate (72).

Abstract translation: 提供高频电磁带隙（EBG）装置（70,90）和制造该装置的方法（100）。 器件（70,90）包括第一衬底（72），其包括形成周期性晶格的多个导电通孔（74）。 第一基板（72）的通孔（74）从第一基板（72）的下表面延伸到第一基板（72）的上表面。 器件（70,90）还包括具有形成周期性晶格的多个导电通孔（78）的第二衬底（76）。 第二基板（76）的通路（78）从第二基板（76）的下表面延伸到第二基板（76）的上表面。 第二基板（76）定位成与第一基板（72）相邻并重叠，使得第二基板（76）的下表面与第一基板（72）的上表面接触， 所述第二基板（76）的多个通孔（78）与所述第一基板（72）的对应的多个通孔（74）接触。

公开(公告)号：EP1631130A3

公开(公告)日：2007-08-08

申请号：EP05018486.0

申请日：2005-08-25

Applicant: HIROSE ELECTRIC CO., LTD.

Inventor： Matsuo, Tsutomu, Hirose Electric Co., Ltd

IPC: H05K1/02 ,  H01L23/528

CPC classification number: H05K1/116 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/18 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/10189 ,  H01L2924/00

Abstract: In a transmission circuit board, ground terminal portions (10) are disposed at every other two rows in both end columns. Each of signal circuit layers (20) includes at least a pair of adjacent signal connecting portions electrically connected to a pair of the wiring portions (21, 22) arranged in parallel in a row direction and the column direction different from those on an adjacent signal circuit layer. Each of the ground layers is electrically connected to at least one of the ground terminal portions (10) in the both end columns.

公开(公告)号：EP1795951A1

公开(公告)日：2007-06-13

申请号：EP06124483.6

申请日：2006-11-21

Applicant: TPO Displays Corp.

Inventor： Liu, Cheng-Hung

IPC: G02F1/13357 ,  G02B6/00 ,  F21V29/00

CPC classification number: F21V29/86 ,  F21K9/00 ,  F21V29/83 ,  G02B6/003 ,  G02B6/0083 ,  G02B6/0085 ,  G02F1/133603 ,  H05K1/0206 ,  H05K3/0061 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/10106

Abstract: A cooling scheme for an LED based back-light in a liquid crystal display (LCD) is disclosed. A circuit board (10) in the LED backlight (300) of the LCD (100) has a thermally (and (optionally) electrically) conductive material (M) arranged to completely fill at least one through-hole (H) joining its front (101) and back (102) surfaces in order to facilitate the efficient removal of heat from at least one LED (40) mounted its the front surface.
The high thermal conductivity material can have a large surface area at the back side of the circuit board in order to further increase heat removal. An additional thermally conducting medium (20) in contact with the material (M) ensures efficient heat transport to a surrounding frame (30), which acts as a heat sink. The holes in the PCB may be located in regions between the LEDs or under them. They may have different sizes. Larger holes may be provided under the LEDs. The material in the holes may also be electrically conducting to allow an electric contact to the LED terminals (41) to be made. The further thermally conducting medium may be a three layer structure, the two outer layers which are electrically insulating sandwiching an electrically conductive middle layer.

Abstract translation: 公开了一种用于液晶显示器（LCD）中的基于LED的背光的冷却方案。 LCD（100）的LED背光源（300）中的电路板（10）具有热（和（任选地）电气的）导电材料（M），其布置成完全填充连接其前部的至少一个通孔（H） （101）和后（102）表面，以便于有效地从安装在其前表面上的至少一个LED（40）去除热量。 高导热性材料可以在电路板的背面具有大的表面积，以便进一步增加散热。 与材料（M）接触的另外的导热介质（20）确保了有效的热传递到作为散热器的周围框架（30）。 PCB中的孔可以位于LED之间或其下的区域中。 他们可能有不同的大小。 可以在LED下面提供更大的孔。 孔中的材料也可以是导电的，以允许与LED端子（41）的电接触。 进一步的导热介质可以是三层结构，两个外层电绝缘夹着导电中间层。

公开(公告)号：EP1621054A1

公开(公告)日：2006-02-01

申请号：EP04728728.9

申请日：2004-04-21

Applicant: Senseair AB

Inventor： MARTIN, Hans Göran Evald ,  HJORT, Klas Anders ,  LINDBERG, Mikael Peter Erik

IPC: H05K3/18

CPC classification number: H05K3/0041 ,  G01K2211/00 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/002 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2203/092 ,  H01L2924/00

Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1), having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10-V60) are chosen having mutually different thermoelectric properties. A material surface-applied to the thin film substrate, coated on both sides (10a, 10b) of the thin film substrate (10), is distributed and/or adapted in order to allow the electrical interconnection of first vias, allocated the first material (M1), with second vias, allocated the second material (M2), and that a first via (V10) included in a series connection and a last via (V60) included in the series connection are serially co-ordinated in order to form an electric thermocouple (100) or other circuit arrangement.

公开(公告)号：EP1615485A1

公开(公告)日：2006-01-11

申请号：EP04726017.9

申请日：2004-04-06

Applicant: IBIDEN CO., LTD.

Inventor： KATO, Shinobu, c/o Ibiden Co., Ltd.

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09609 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: In a core substrate 30, a ground through hole 36E and a power through hole 36P are disposed in the grid formation, so that electromotive force induced in X direction and Y direction cancel out each other. As a result, even if mutual inductance is reduced and a high frequency IC chip is loaded, electric characteristic and reliability can be improved without generating malfunction or error.

Abstract translation: 在核心基板30中，以网格形式设置接地通孔36E和电源通孔36P，使得在X方向和Y方向上感应出的电动势彼此抵消。 结果，即使互感减小并且加载了高频IC芯片，也可以改善电特性和可靠性而不产生故障或错误。

公开(公告)号：EP0988576B1

公开(公告)日：2002-05-08

申请号：EP98931120.4

申请日：1998-06-12

Applicant: Papyron B.V.

Inventor： RUITER, Jacobus, Christiaan, Gerardus, Maria ,  TERLOUW, Erik, Maarten ,  HADZIIOANNOU, Georges ,  BROUWER, Hendrik-Jan

IPC: G02F1/136 ,  H05K3/40 ,  H01B1/20

CPC classification number: H05K3/4038 ,  G02F1/1333 ,  G02F1/1345 ,  G02F1/135 ,  G02F1/1362 ,  H01B1/22 ,  H05K1/0287 ,  H05K3/105 ,  H05K2201/09609 ,  H05K2203/105

Abstract: Substrate (7; 7'; 10) and devices including such a substrate, the substrate having a first surface and a second surface extending substantially in parallel to the first surface, the substrate being of a material of a first conductivity and provided with a plurality of electrically conducting channels (21) which are extending exclusively in a direction perpendicular to the first and second surfaces, said channels having a second conductivity substantially larger than the first conductivity, the substrate being provided with at least one electrode (42) on either one of the first and second surfaces, contacting at least one of said channels, the at least one electrode (42) having a predetermined minimum dimension (D) in a contact area (A) with the substrate, and mutual distances between adjacent ones of the plurality of channels (21) being smaller than said minimum dimension of said at least one electrode (42).

Abstract translation: 基板（7; 7“; 10）和设备包括寻求一个基板，具有第一表面和第二表面在大致平行地延伸于所述第一表面的衬底，所述衬底是第一导电性的材料制成，并设置有多个 电的传导通道（21），其垂直独占延伸的方向上的第一和第二表面，所述具有第二导电实质上大于所述第一导电较大的通道，所述基板被设置在任一个上的至少一个电极（42） 所述第一和第二表面，接触所述通道中的至少一个，所述至少一个电极（42）具有预定的最小尺寸（D）的基材中的接触面积（A）与，与的相邻者之间的相互距离的 比中的至少所述最小尺寸较小的通道（21）的多个所述一个电极（42）。

公开(公告)号：EP0811245A4

公开(公告)日：1998-11-18

申请号：EP96936229

申请日：1996-09-27

Applicant: TEXAS INSTRUMENTS INC

Inventor： PETERSON ROBERT K ,  PURINTON DONALD L ,  MERRITT GORDON D ,  ABLES BILLY D

IPC: H01L23/36 ,  H01L23/49 ,  H01L23/492 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K3/46 ,  H01L23/34

CPC classification number: H01L25/0657 ,  H01L23/4922 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/01 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/3011 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/0116 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K2201/10378

Abstract: An assembly of two or more microelectronic parts, wherein electrical and/or thermal interconnection between the parts is achieved by means of multiple, discrete, conductive nanoscopic fibrils (15) or tubules (15) fixed within the pores of an insulating film (16). Such a film is said to have anisotropic electrical conductivity, i.e., Z-axis conductivity, with little or no conductivity in the other directions.

Abstract translation: 两个或更多个微电子部件的组件，其中部件之间的电和/或热互连通过固定在绝缘膜（16）的孔内的多个分立导电的纳米级原纤（15）或小管（15）来实现， 。 据说这种膜具有各向异性导电性，即Z轴导电性，在其它方向上几乎没有或没有导电性。

公开(公告)号：EP0834921A2

公开(公告)日：1998-04-08

申请号：EP97203302.1

申请日：1992-12-30

Applicant: TESSERA, INC.

Inventor： Distefano, Thomas H. ,  Khandros, Igor ,  Grube, Gary W. ,  Ehrenberg, Scott G.

IPC: H01L23/538

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H01L2924/00

Abstract: The invention relates to a method of making a multi-layer circuit assembly. Said method comprises the steps of providing a first circuit panel (544) having a dielectric body with oppositely directed top and bottom surfaces, contacts (538) on its top surface at locations of a first pattern, terminals (530) on its bottom surface, and through-conductors (527) electrically connected to said terminals and extending to the top surface of the panel, and a second circuit panel (562) having a dielectric body with a bottom surface and terminals (530) at locations of said first pattern on the bottom surface of such panel, said providing step including the step of customizing said first circuit panel by selectively treating the top surface of such panel so that less than all of the through conductors of such panel are connected to contacts of such panel; stacking said circuit panels in superposed, top-surface to bottom surface relation so that the top surface of said first circuit panel faces the bottom surface of said second circuit panel at a first interface and said first patterns on said facing surfaces are in registration with one another, with said contacts of said first panel being aligned with said terminals of said second panel at least some locations of said inregistration patterns; and non-selectively connecting all of said aligned contacts and terminals at said interface, whereby less than all of said through conductors of said customized panel are connected to terminals of said adjacent panel. The invention also relates to a multi-layer circuit assembly.

Abstract translation: 本发明涉及一种制造多层电路组件的方法。 所述方法包括以下步骤：提供具有电介质体的第一电路面板（544），所述电介质体具有相反指向的顶部和底部表面，其顶表面上的第一图案位置处的触点（538），其底表面上的端子（530） 和电连接到所述端子并延伸到所述面板的顶表面的贯穿导体（527），以及第二电路板（562），所述第二电路板（562）具有电介质体，所述电介质体具有底表面和在所述第一图案的位置处的端子 所述提供步骤包括定制所述第一电路板的步骤，所述步骤通过选择性地处理所述板的顶部表面以使得所述板的所有贯通导体都少于所述板的触点连接; 将所述电路面板叠置成叠置的顶面到底面关系，使得所述第一电路面板的顶面在第一界面处面向所述第二电路面板的底面，并且在所述面对的表面上的所述第一图案与一个 另一方面，所述第一面板的所述触点与所述第二面板的所述端子对准所述对齐图案的至少一些位置; 并且在所述接口处非选择性地连接所有所述对齐的触点和端子，由此所述定制面板的少于所有的所述贯通导体连接到所述相邻面板的端子。 本发明还涉及一种多层电路组件。

公开(公告)号：EP0166289B1

公开(公告)日：1990-05-23

申请号：EP85107130.8

申请日：1985-06-11

Applicant: International Business Machines Corporation

Inventor： Kraus, Charles John ,  Stoller, Herbert Ivan ,  Wu, Leon Li-Heng

IPC: H05K1/00 ,  H01L23/52

CPC classification number: H01L23/5383 ,  H01L2224/16225 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/4629 ,  H05K2201/09609

公开(公告)号：EP0236830A3

公开(公告)日：1988-09-14

申请号：EP87102549

申请日：1987-02-23

Applicant: CIRCUITGRAPH, S.L.

Inventor： Melero, Pedro Valenciano

IPC: H05K01/02

CPC classification number: H05K3/326 ,  H05K1/119 ,  H05K2201/09609 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/1059

Abstract: Eine Grundplatte (1) für elektrische Stromkreise besteht aus einem isolierenden, mit Durchgangslöchern (2) versehenen Schicht körper. Damit die elektrischen Stromkreise einfacher und schneller hergestellt werden können, sind die Durchgangslöcher (2) kegelstumpfförmig, wobei der größere Durchmesser des Kegel stumpfs größer und der kleinere Durchmesser des Kegelstumpfs kleiner ist als der Durchmesser der Anschlußteile der zu verbin denden elektrischen Bauteile (Fig. 2).

Abstract translation: 用于电路的基板（1）由设有穿孔（2）的绝缘层状体构成。 为了使电路可以更加简单和快速地制造，穿孔（2）是截头圆锥形的，截头锥体的较大直径较大，截头圆锥体的直径小于直径 要连接的电气元件的连接部分（图2）。