公开(公告)号：KR100809327B1

公开(公告)日：2008-03-05

申请号：KR1020060075816

申请日：2006-08-10

Applicant: 삼성전자주식회사

Inventor： 정형석 ,  이종호 ,  한성기 ,  이호 ,  임하진

IPC: H01L21/336

CPC classification number: H01L21/823807

Abstract: 반도체 소자 및 그 제조 방법이 제공된다. 본 발명의 반도체 소자는 NMOS 트랜지스터 영역 및 PMOS 트랜지스터 영역을 포함하는 반도체 기판, PMOS 트랜지스터 영역에 위치하는 PMOS 트랜지스터로서, P형 소스/ 드레인 영역 및 P형 소스/드레인 영역 사이의 SiGe 채널영역 상에 위치하는 고유전율의 게이트 절연막 상에 형성된 게이트 전극을 포함하는 PMOS 트랜지스터 및 NMOS 트랜지스터 영역에 위치하는 NMOS 트랜지스터로서, N형 소스/드레인 영역 사이의 Si 채널영역 상에 형성되며 고유전율의 게이트 절연막, 게이트 절연막 상에 형성된 게이트 전극을 포함하는 NMOS 트랜지스터를 포함한다.
SiGe 채널영역, SiGe 에피택셜층, 고유전율 게이트 절연막,

公开(公告)号：KR1020080014307A

公开(公告)日：2008-02-14

申请号：KR1020060075816

申请日：2006-08-10

Applicant: 삼성전자주식회사

Inventor： 정형석 ,  이종호 ,  한성기 ,  이호 ,  임하진

IPC: H01L21/336

CPC classification number: H01L21/823807

Abstract: A semiconductor device and a method for fabricating the same are provided to improve the characteristic such as threshold voltage and carrier mobility of the semiconductor device by forming a PMOS transistor on a SiGe channel region and an NMOS transistor on a Si channel region. A semiconductor device comprises a semiconductor substrate(100), a PMOS transistor(120P), and an NMOS transistor(120N). The semiconductor substrate includes a PMOS transistor region(I) and an NMOS transistor region(II). The PMOS transistor is positioned in the PMOS transistor region, and has P-type source/drain regions(129P) and a gate electrode(126) formed on a gate insulating film(121) having high dielectric constant positioned in a SiGe channel region(A) between the P-type source/drain regions. The NMOS transistor is positioned in the NMOS transistor region, and has the gate electrode formed on the gate insulating film having high dielectric constant positioned in a Si channel region(B) between N-type source/drain regions(129N).

Abstract translation: 提供一种半导体器件及其制造方法，以通过在Si沟道区上形成PMOS晶体管和Si沟道区上的NMOS晶体管来提高半导体器件的阈值电压和载流子迁移率等特性。 半导体器件包括半导体衬底（100），PMOS晶体管（120P）和NMOS晶体管（120N）。 半导体衬底包括PMOS晶体管区域（I）和NMOS晶体管区域（II）。 PMOS晶体管位于PMOS晶体管区域中，并且具有P型源极/漏极区域（129P）和形成在位于SiGe沟道区域中的具有高介电常数的栅极绝缘膜（121）上的栅电极（126） A）在P型源/漏区之间。 NMOS晶体管位于NMOS晶体管区域中，并且在位于N型源极/漏极区域（129N）之间的Si沟道区域（B）中的具有高介电常数的栅极绝缘膜上形成栅电极。

公开(公告)号：KR1020070002864A

公开(公告)日：2007-01-05

申请号：KR1020050058559

申请日：2005-06-30

Applicant: 삼성전자주식회사

Inventor： 김민주 ,  이종호 ,  한성기 ,  정형석

IPC: H01L21/336

CPC classification number: H01L21/823842 ,  H01L21/28194 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: A semiconductor device with an CMOS transistor and a manufacturing method thereof are provided to obtain optimum Vt values from NMOS and PMOS transistors using an improved gate electrode including a predetermined metal alloy layer. A semiconductor device includes a CMOS transistor which is composed of a first MOS transistor with a first channel of a first conductive type and a second MOS transistor with a second channel of a second conductive type. The first MOS transistor(110) is composed of a first gate insulating layer(112) and a gate electrode. The gate electrode includes a first metal alloy layer(118) composed of a first metal(114) and a second metal(116).

Abstract translation: 提供具有CMOS晶体管的半导体器件及其制造方法，以使用包括预定金属合金层的改进的栅电极从NMOS和PMOS晶体管获得最佳Vt值。 半导体器件包括由具有第一导电类型的第一沟道的第一MOS晶体管和具有第二导电类型的第二沟道的第二MOS晶体管构成的CMOS晶体管。 第一MOS晶体管（110）由第一栅极绝缘层（112）和栅极电极构成。 栅电极包括由第一金属（114）和第二金属（116）构成的第一金属合金层（118）。

公开(公告)号：KR100662850B1

公开(公告)日：2007-01-02

申请号：KR1020060010123

申请日：2006-02-02

Applicant: 삼성전자주식회사

Inventor： 정영수 ,  한성기 ,  정형석 ,  이형익

IPC: H01L21/336

Abstract: A semiconductor device with plural metal layers stacked is provided to suppress a reaction between a gate oxide layer and a metal layer by depositing the metal layer using the same material as that of the gate oxide layer. A semiconductor device includes a substrate(110), a gate oxide layer(120) of high dielectric deposited on the substrate, a first metal layer(131) deposited on the gate oxide layer, a second metal layer(132) deposited on the first metal layer, a third metal layer(133) deposited on the second metal layer, and a polycrystalline silicon layer(140) deposited on the third metal layer. The first metal layer is made of the same material as the gate oxide layer. The polycrystalline silicon layer forms a gate electrode together with the first to third metal layers.

Abstract translation: 提供具有堆叠的多个金属层的半导体器件，以通过使用与栅极氧化物层相同的材料沉积金属层来抑制栅极氧化物层和金属层之间的反应。 一种半导体器件，包括衬底（110），沉积在衬底上的高电介质的栅极氧化物层（120），沉积在栅极氧化物层上的第一金属层（131），沉积在第一金属层 金属层，沉积在第二金属层上的第三金属层（133）以及沉积在第三金属层上的多晶硅层（140）。 第一金属层由与栅极氧化物层相同的材料制成。 多晶硅层与第一至第三金属层一起形成栅电极。

公开(公告)号：KR100553714B1

公开(公告)日：2006-02-24

申请号：KR1020040054860

申请日：2004-07-14

Applicant: 삼성전자주식회사

Inventor： 선민철 ,  구자흠 ,  정석우 ,  한성기 ,  김민주 ,  노관종

IPC: H01L21/336

CPC classification number: H01L21/28518 ,  H01L29/665

Abstract: 자기정렬 실리사이드층을 가지는 반도체 소자 및 그 제조방법을 제공한다. 이 소자는 기판에 형성되어 활성영역을 한정하는 소자분리막과 상기 활성영역 상부를 가로지르는 게이트 패턴을 포함한다. 상기 게이트 패턴의 양 측벽에 스페이서 절연막이 형성된다. 상기 게이트 패턴의 상부(upper portion)에 제 1 및 제 2 살리사이드층(salicide layer)가 형성되고, 상기 스페이서 절연막과 상기 소자분리막 사이의 활성영역에 각각 제 1 살리사이드층(salicide layer)이 형성된다. 상기 게이트 패턴 상부의 제 1 및 제 2 살리사이드층은 번갈아 서로 연결되어 형성된다. 폭이 좁은 게이트 패턴에 제 1 살리사이드층이 집괴되어 형성된 후 제 2 살리사이드층으로 패치하여 이어진 살리사이드층을 형성할 수 있다.

公开(公告)号：KR1020000010383A

公开(公告)日：2000-02-15

申请号：KR1019980031272

申请日：1998-07-31

Applicant: 삼성전자주식회사

Inventor： 한성기

IPC: G06T3/00

Abstract: PURPOSE: An article arrangement method of computerized typesetting system is provided to improve typesetting ability by arranging articles along the layout of the specified object in an image. CONSTITUTION: The article arrangement method comprises the steps of making a paper space to arrange articles as bitmap and setting a bit value of each bit image as 1, making layout information of the specified object in an image information to be arranged with the articles, and setting bit value of the bit image related to the specified object as 1, logic-calculating a bit value of each bit inter-corresponding between the paper space image and the layout bit image, arranging an equivalent article in a region in which the bit value of the bit image is set as 0 in a bitmap acquired due to the result of logic-calculating.

Abstract translation: 目的：提供一种电脑排版系统的文章排列方法，通过沿图像中的指定对象的布局布置文章来提高排版能力。 构成：文章排列方法包括以下步骤：使纸张空间作为位图布置，并将每个位图的位值设置为1，使得指定对象的布局信息与图像信息一起排列，并且， 将与指定对象相关的比特图像的比特值设置为1，逻辑计算纸张空间图像和布局比特图像之间相互对应的每个比特的比特值，将等价物品排列在比特值 由于逻辑运算的结果，位图中的位图被设置为0。

公开(公告)号：KR1020160095399A

公开(公告)日：2016-08-11

申请号：KR1020150016621

申请日：2015-02-03

Applicant: 삼성전자주식회사

Inventor： 김완돈 ,  권오성 ,  나훈주 ,  손혁준 ,  송재열 ,  한성기 ,  현상진

IPC: H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/7831 ,  H01L29/7843 ,  H01L29/785

Abstract: 반도체장치및 그제조방법이제공된다. 상기반도체장치는제1 핀과, 상기제1 핀상에형성된제1 트렌치와, 상기제1 트렌치의내벽을따라서형성된제1 유전막과, 상기제1 트렌치내에상기제1 유전막상에형성된제1 도전형의제1 일함수금속막을포함하는제1 핀형트랜지스터; 제2 핀과, 상기제2 핀상에형성된제2 트렌치와, 상기제2 트렌치의내벽을따라서형성된제2 유전막과, 상기제2 트렌치내에상기제2 유전막상에형성된제1 도전형의제2 일함수금속막을포함하는제2 핀형트랜지스터; 및제3 핀과, 상기제3 핀상에형성된제3 트렌치와, 상기제3 트렌치의내벽을따라서형성된제3 유전막과, 상기제3 트렌치내에상기제3 유전막상에형성된제1 도전형의제3 일함수금속막을포함하는제3 핀형트랜지스터를포함하고, 상기제1 유전막은일함수조절물질을포함하고, 상기제2 유전막은상기일함수조절물질을비포함하고, 상기제1 일함수금속막의제1 두께와, 상기제3 일함수금속막의제3 두께는서로다르다.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：第一引脚型晶体管，包括第一引脚，形成在第一引脚上的第一沟槽，沿着第一沟槽的内壁形成的第一电介质膜，以及形成第一导电类型的第一功函数金属膜 在第一沟槽中的第一介电膜上; 第二引脚型晶体管，包括第二引脚，形成在第二引脚上的第二沟槽，沿着第二沟槽的内壁形成的第二电介质膜，以及形成在第二电介质上的第一导电类型的第二功函数金属膜 第二沟中的电影; 以及第三引脚型晶体管，包括第三引脚，形成在第三引脚上的第三沟槽，沿着第三沟槽的内壁形成的第三电介质膜，以及形成在第三引脚上的第三导电类型的第三功函数金属膜 第三沟槽中的介电膜。 第一电介质膜包括功函调整材料。 第二电介质膜不包括功函数调整材料。 第一功函数金属膜的第一厚度和第三功函数金属膜的第三厚度彼此不同。

公开(公告)号：KR1020140034019A

公开(公告)日：2014-03-19

申请号：KR1020120126839

申请日：2012-11-09

Applicant: 삼성전자주식회사

Inventor： 김주연 ,  최현민 ,  한성기 ,  김제돈

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/28518 ,  H01L21/823462 ,  H01L29/66545

Abstract: Provided is a method for manufacturing a semiconductor device with improved reliability by using a silicon electrode in a region which requires reliability within a semiconductor device and using a metal electrode in a region which requires a high operation speed. The method for manufacturing a semiconductor device includes the steps of: forming a first gate pattern and a dummy gate pattern in a first active region and a second active region, respectively, on a substrate; forming a second gate pattern including a second gate insulation film and a metal gate electrode on the exposed substrate surface while the first gate pattern includes a first gate insulation film and a silicon gate electrode and the substrate surface of the second active region is exposed by removing the dummy gate pattern; and forming a gate silicide on the silicon gate electrode after forming the second gate pattern while the thickness of the first gate insulation film is greater than the thickness of the second insulation film.

Abstract translation: 提供一种通过在半导体器件中需要可靠性的区域中使用硅电极并且在需要高操作速度的区域中使用金属电极来制造具有可靠性提高的半导体器件的方法。 制造半导体器件的方法包括以下步骤：在衬底上分别在第一有源区和第二有源区中形成第一栅极图案和伪栅极图案; 在所述暴露的基板表面上形成包括第二栅极绝缘膜和金属栅极的第二栅极图案，同时所述第一栅极图案包括第一栅极绝缘膜和硅栅电极，并且所述第二有源区的所述基板表面通过去除 虚拟门模式; 以及在形成所述第二栅极图案之后在所述硅栅极上形成栅极硅化物，同时所述第一栅极绝缘膜的厚度大于所述第二绝缘膜的厚度。

公开(公告)号：KR1020120140112A

公开(公告)日：2012-12-28

申请号：KR1020110059792

申请日：2011-06-20

Applicant: 삼성전자주식회사

Inventor： 송재열 ,  한정희 ,  현상진 ,  한성기 ,  손혁준

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to reduce a leakage current by thickening a second high-k layer than a third high-k layer. CONSTITUTION: A trench is formed by removing a dummy gate pattern. A laminate insulation layer is formed in the trench for forming g gate. A first high-k layer is formed(S1010). A second high-k layer is formed by thermally processing the first high-k layer(S1020). A third high-k layer is formed on the second high-k layer after a thermal process(S1030). The relative permittivity of the third high-k layer is higher than the relative permittivity of the second high-k and the dielectric constant of the third high-k layer is 40 or more. A gate electrode is formed in the trench for forming a gate.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过使第二高k层比第三高k层增厚来减少泄漏电流。 构成：通过去除虚拟栅极图案形成沟槽。 在用于形成栅极的沟槽中形成层压绝缘层。 形成第一高k层（S1010）。 通过热处理第一高k层形成第二高k层（S1020）。 在热处理之后，在第二高k层上形成第三高k层（S1030）。 第三高k层的相对介电常数高于第二高k的相对介电常数，第三高k层的介电常数为40以上。 在用于形成栅极的沟槽中形成栅电极。

公开(公告)号：KR100814372B1

公开(公告)日：2008-03-18

申请号：KR1020070007278

申请日：2007-01-24

Applicant: 삼성전자주식회사

Inventor： 정형석 ,  이종호 ,  한성기 ,  최윤기 ,  임하진

IPC: H01L21/336

CPC classification number: H01L21/823842 ,  H01L21/28026 ,  H01L29/49

Abstract: A method for fabricating a semiconductor device is provided to avoid damage to an active region of a substrate adjacent to a gate structure and prevent a gate insulation layer from being damaged by sequentially performing a dry etch process, a selective wet etch process and a dry etch process on conductive layers with different thicknesses formed in NMOS and PMOS regions. A substrate is prepared which includes a first channel of a first conductivity type and a second channel of a second conductivity type different from the first conductivity type. A gate insulation layer is formed on the substrate. A first conductive layer including a first metal is formed on the gate insulation layer. A second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed on the second channel. The crystalline structure of the second conductive layer can be weakened by plasma or ion implantation. The second conductive layer is partially removed by a wet etch process to form a second conductive layer pattern on the second channel.

Abstract translation: 提供了一种用于制造半导体器件的方法，以避免损坏与栅极结构相邻的衬底的有源区，并且通过依次执行干蚀刻工艺，选择性湿蚀刻工艺和干蚀刻来防止栅绝缘层受损 在NMOS和PMOS区域中形成具有不同厚度的导电层的工艺。 制备包括第一导电类型的第一沟道和不同于第一导电类型的第二导电类型的第二沟道的衬底。 在基板上形成栅极绝缘层。 包括第一金属的第一导电层形成在栅绝缘层上。 在形成在第二通道上的第一导电层上形成包括不同于第一金属的第二金属的第二导电层。 通过等离子体或离子注入可以削弱第二导电层的晶体结构。 通过湿式蚀刻工艺部分去除第二导电层，以在第二通道上形成第二导电层图案。