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公开(公告)号：KR1020160033865A
公开(公告)日：2016-03-29
申请号：KR1020140124472
申请日：2014-09-18
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/335
CPC classification number: H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02255 , H01L21/302 , H01L21/30604 , H01L21/3065 , H01L21/3086 , H01L29/165 , H01L29/7848 , H01L29/785 , H01L29/7831
Abstract: 본발명의일 측면은, 기판과, 상기기판상에배치되며상기기판에인접한제1 면과상기제1 면의반대면인제2 면을갖는소자분리막및 상기기판상에배치되며, 상기소자분리막의제2 면상으로돌출된측벽을갖는제1 영역과상기제1 영역상에위치하며상부면을갖는제2 영역을포함하는적어도하나의활성핀(fin)을포함하고, 상기제1 영역은상기소자분리막의제2 면에인접한제1 폭과상기제2 영역에인접한제2 폭을가지며, 상기제2 폭은상기제1 폭의 60% 이상의크기를갖는반도체소자를제공한다.
Abstract translation: 为了减少短信道效应，根据本发明的一个方面，半导体器件包括衬底，器件隔离层，其布置在衬底上并且具有与衬底相邻的第一表面和面向第一表面的第二表面 以及至少一个有源鳍片，其布置在衬底上并且包括具有突出到器件隔离层的第二表面的侧壁的第一区域和位于第一区域中并具有上表面的第二区域。 第一区域具有与器件隔离层的第二表面相邻的第一宽度和与第二区域相邻的第二宽度。 第二宽度比第一宽度宽至少60％。
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公开(公告)号：KR1020150066133A
公开(公告)日：2015-06-16
申请号：KR1020130151305
申请日：2013-12-06
Applicant: 삼성전자주식회사
CPC classification number: B23K9/04 , B22F2009/045 , B23K9/06 , C22C1/002 , C22C1/03 , C22C45/00 , C22C45/08 , C22C2200/02 , H01B1/22
Abstract: 금속유리와용매를포함하는슬러리를준비하는단계, 압축공기가통과되는영역에상기슬러리를공급하는단계, 상기압축공기를단열팽창시켜상기금속유리를액적화하는단계, 그리고상기액적화된금속유리를분쇄하는단계를포함하는금속유리의분쇄방법, 상기방법으로얻어진분쇄된금속유리, 상기분쇄된금속유리를포함하는도전성페이스트및 상기도전성페이스트로부터형성된전극을포함하는전자소자에관한것이다.
Abstract translation: 本发明涉及金属玻璃粉碎金属玻璃，导电浆料和电子设备的粉碎方法。 粉碎金属玻璃的方法包括以下步骤：制备包括金属玻璃和溶剂的浆料; 将浆料供应到压缩空气通过的区域; 绝热膨胀压缩空气液化金属玻璃; 粉碎液化金属玻璃。 导电性糊料和包含由导电性糊料形成的电极的电子器件包含：通过该方法得到的金属玻璃; 和粉碎的金属玻璃。
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公开(公告)号：KR1020080079940A
公开(公告)日：2008-09-02
申请号：KR1020070020593
申请日：2007-02-28
Applicant: 삼성전자주식회사
IPC: H01L27/146
CPC classification number: H01L29/517 , H01L21/28088 , H01L21/823842 , H01L29/4966
Abstract: A CMOS semiconductor device and a manufacturing method thereof are provided to prevent reduction of performance by eliminating a reaction between heterogeneous materials. A CMOS semiconductor device includes an nMOS region and a pMOS region. A gate including a poly-Si capping layer(5) and a metal nitride layer(3a,3b) deposited under the poly-Si capping layer are formed in the nMOS region and the pMOS region, respectively. A gate insulating layer(2) is formed in a lower part of each gate of the nMOS region and the pMOS region. The metal nitride layers of the nMOS region and the pMOS region are made of a homogeneous material. The metal nitride layers of the nMOS region and the pMOS region has different work functions according to a concentration difference of impurities.
Abstract translation: 提供CMOS半导体器件及其制造方法，以通过消除异质材料之间的反应来防止性能降低。 CMOS半导体器件包括nMOS区和pMOS区。 在nMOS区域和pMOS区域分别形成包括多晶硅覆盖层（5）和沉积在多晶硅覆盖层下方的金属氮化物层（3a，3b）的栅极。 栅极绝缘层（2）形成在nMOS区域和pMOS区域的每个栅极的下部。 nMOS区域和pMOS区域的金属氮化物层由均质材料制成。 根据杂质的浓度差，nMOS区域和pMOS区域的金属氮化物层具有不同的功函数。
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公开(公告)号：KR1020030068735A
公开(公告)日：2003-08-25
申请号：KR1020020008332
申请日：2002-02-16
Applicant: 삼성전자주식회사
IPC: G02B6/44
Abstract: PURPOSE: An optical fiber cable including an optical fiber bundle is provided to minimize an outside diameter by reducing the usage of tensile members and using optical fiber of a spiral structure and the optical fiber bundle having a circular section. CONSTITUTION: An optical fiber cable including an optical fiber bundle includes an optical fiber having a plurality of cores and an external coating layer(290) for protecting the optical fiber. Each optical fiber includes a bundle of optical fibers(230) and a coating layer(240). The bundle of optical fibers are formed by twisting spirally the optical fibers to a longitudinal direction. The coating layer is used for covering the bundle of optical fibers. An optical fiber bundle(250) is included in the external coating layer. The optical fiber bundle has a circular section. A re-coating layer is coated around the coating layer.
Abstract translation: 目的：提供一种包括光纤束的光缆，通过减少拉伸构件的使用和使用螺旋结构的光纤和具有圆形截面的光纤束来最小化外径。 构成：包括光纤束的光缆包括具有多个芯的光纤和用于保护光纤的外部涂层（290）。 每个光纤包括一束光纤（230）和一个涂层（240）。 光纤束通过将光纤螺旋地沿纵向方向旋转而形成。 涂层用于覆盖光纤束。 光纤束（250）包含在外部涂层中。 光纤束具有圆形截面。 在涂层周围涂覆再涂层。
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公开(公告)号：KR1020150061698A
公开(公告)日：2015-06-05
申请号：KR1020130145486
申请日：2013-11-27
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66795 , H01L21/823431 , H01L21/823481 , H01L29/165 , H01L29/66545 , H01L29/7848
Abstract: 반도체장치가제공된다. 반도체장치는, 기판으로부터돌출된형상으로제1 방향으로정렬되어연장되고, 상기제1 방향으로서로이격되는제1 및제2 핀, 상기제1 및제2 핀사이에, 상기제1 방향과교차하는제2 방향으로연장되어배치된필드절연막, 상기필드절연막상에형성된식각정지막패턴, 및상기식각정지막패턴상에형성된더미게이트(dummy gate) 구조체를포함한다.
Abstract translation: 提供半导体器件。 半导体器件包括延伸成在第一方向上以从基板突出的形状延伸并在第一方向上彼此分离的第一和第二销钉; 场绝缘膜，沿与第一和第二销之间的第一方向交叉的第二方向延伸; 形成在所述绝缘膜上的蚀刻停止膜图案; 以及形成在蚀刻停止膜图案上的虚拟栅极结构。
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Patent Agency Ranking
公开(公告)号：KR1020080097006A
公开(公告)日：2008-11-04
申请号：KR1020070042057
申请日：2007-04-30
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/42332 , H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/513 , H01L29/7881 , H01L29/792 , B82Y10/00
Abstract: A non-volatile memory device is provided to have the excellent electron storage capability by including the nano dots. The manufacturing method of the non-volatile memory device includes the step of forming the tunnel insulating layer(110) in the top of the substrate; the step of forming the charge storage layer(127) including the lanthanide nano dots(125) on the tunnel insulating layer; the step of forming the control gate layer on the charge storage layer; the step of forming a gate stack by patterning the control gate layer and the charge storage layer.
Abstract translation: 提供非易失性存储器件以通过包括纳米点具有优异的电子存储能力。 非易失性存储器件的制造方法包括在衬底的顶部形成隧道绝缘层（110）的步骤; 在隧道绝缘层上形成包含镧系元素纳米点（125）的电荷存储层（127）的步骤; 在电荷存储层上形成控制栅极层的步骤; 通过图案化控制栅极层和电荷存储层来形成栅极堆叠的步骤。
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公开(公告)号：KR100662850B1
公开(公告)日：2007-01-02
申请号：KR1020060010123
申请日：2006-02-02
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: A semiconductor device with plural metal layers stacked is provided to suppress a reaction between a gate oxide layer and a metal layer by depositing the metal layer using the same material as that of the gate oxide layer. A semiconductor device includes a substrate(110), a gate oxide layer(120) of high dielectric deposited on the substrate, a first metal layer(131) deposited on the gate oxide layer, a second metal layer(132) deposited on the first metal layer, a third metal layer(133) deposited on the second metal layer, and a polycrystalline silicon layer(140) deposited on the third metal layer. The first metal layer is made of the same material as the gate oxide layer. The polycrystalline silicon layer forms a gate electrode together with the first to third metal layers.
Abstract translation: 提供具有堆叠的多个金属层的半导体器件，以通过使用与栅极氧化物层相同的材料沉积金属层来抑制栅极氧化物层和金属层之间的反应。 一种半导体器件，包括衬底（110），沉积在衬底上的高电介质的栅极氧化物层（120），沉积在栅极氧化物层上的第一金属层（131），沉积在第一金属层 金属层，沉积在第二金属层上的第三金属层（133）以及沉积在第三金属层上的多晶硅层（140）。 第一金属层由与栅极氧化物层相同的材料制成。 多晶硅层与第一至第三金属层一起形成栅电极。
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公开(公告)号：KR1020050008076A
公开(公告)日：2005-01-21
申请号：KR1020030047914
申请日：2003-07-14
Applicant: 삼성전자주식회사
IPC: G02B6/44
CPC classification number: G02B6/4432
Abstract: PURPOSE: An indoor optical fiber cable is provided to minimize the generation of after shrinkage in response to the temperature change by controlling the lay ratio of tight buffer optical fiber in place of providing the central strength member. CONSTITUTION: An indoor optical fiber cable includes a plurality of tight buffer optical fibers(420), an auxiliary strength member(430) and an external coating portion(410). The tight buffer optical fibers are encompassed by the auxiliary strength member. The external coating portion encompasses the auxiliary strength member. And, the indoor optical fiber cable is characterized in that the tight buffer optical fibers have a lay ratio between -0.3% to 0.3% for the external coating portion.
Abstract translation: 目的：提供一种室内光纤电缆，用于通过控制紧密缓冲光纤的铺设率来代替提供中心强度构件，以最小化响应于温度变化的收缩后的产生。 构成：室内光纤电缆包括多个紧密缓冲光纤（420），辅助加强部件（430）和外部涂覆部分（410）。 紧密缓冲光纤被辅助强度构件包围。 外部涂覆部分包括辅助强度构件。 并且，室内光纤电缆的特征在于，紧密缓冲光纤对于外部涂布部分具有-0.3％至0.3％的铺设比。
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公开(公告)号：KR101341571B1
公开(公告)日：2013-12-16
申请号：KR1020070042057
申请日：2007-04-30
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/42332 , H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/513 , H01L29/7881 , H01L29/792
Abstract: 비휘발성메모리소자및 그제조방법이개시된다. 상기소자는란탄계나노닷을포함하는전하저장층을갖고, 상기방법은질소분위기의열처리를통해금속나노닷을갖는전하저장층을형성할수 있다. 따라서, 용이한방법으로우수한전하저장능력을갖는소자가제공될수 있다.
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公开(公告)号：KR100617745B1
公开(公告)日：2006-08-28
申请号：KR1020040039222
申请日：2004-05-31
Applicant: 삼성전자주식회사
IPC: G02B6/44
CPC classification number: G02B6/4483 , G02B6/4411 , G02B6/4494
Abstract: 본 발명에 따른 하나 이상의 튜브들과, 상기 튜브들을 바인딩하기 위한 외부 피복을 포함하는 광섬유 케이블에 있어서, 상기 각 튜브는 하나 이상의 광섬유들과, 상기 광섬유들을 묶기 위한 피복과, 상기 광섬유들 간의 정전 현상을 방지하기 위해서 상기 광섬유들의 사이에 도포되는 틱소트로픽 화합물로 이루어진 정전 방지액을 포함한다.
광섬유, 광섬유 케이블, 정전기
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