公开(公告)号：KR1020030033672A

公开(公告)日：2003-05-01

申请号：KR1020010065755

申请日：2001-10-24

Applicant: 삼성전자주식회사

Inventor： 김정욱 ,  홍진기 ,  박지순

IPC: H01L21/336

Abstract: PURPOSE: A method for forming a gate electrode of a semiconductor device and a gate electrode using the same are provided to improve operation speed by forming a minus sloped gate electrode. CONSTITUTION: A stopping oxide layer and an insulation layer are sequentially formed on a semiconductor substrate(30) having a source and drain electrode(32,34). After forming a photoresist pattern on the insulation layer, an insulation pattern having a hole is formed by etching the insulation layer using reaction gas for generating polymers. At this time, the width of the upper portion of the hole is larger than that of the lower portion of the hole. After removing the photoresist pattern, a conductive layer is filled into the hole of the insulation pattern. A polishing process is carried out with the conductive layer in order to expose the insulation pattern. A minus sloped gate electrode(48) is formed by removing the insulation pattern.

Abstract translation: 目的：提供一种用于形成半导体器件的栅电极和使用其的栅电极的方法，以通过形成负斜电栅电极来提高操作速度。 构成：在具有源极和漏极（32,34）的半导体衬底（30）上依次形成停止氧化物层和绝缘层。 在绝缘层上形成光致抗蚀剂图案之后，通过使用用于产生聚合物的反应气体蚀刻绝缘层来形成具有孔的绝缘图案。 此时，孔的上部的宽度大于孔的下部的宽度。 在除去光致抗蚀剂图案之后，将导电层填充到绝缘图案的孔中。 为了露出绝缘图案，用导电层进行抛光处理。 通过去除绝缘图案形成负斜面栅电极（48）。

公开(公告)号：KR1020030017731A

公开(公告)日：2003-03-04

申请号：KR1020010050718

申请日：2001-08-22

Applicant: 삼성전자주식회사

Inventor： 손정훈 ,  홍진기 ,  김민

IPC: H01L21/28

Abstract: PURPOSE: A method for forming wires of a semiconductor device is provided to improve a yield of a semiconductor by forming a blocking layer in a process for forming an electric wire. CONSTITUTION: The first insulating layer(22) including the first conductive pattern(24) is formed on a semiconductor substrate(20). A blocking layer(26a) is formed on an upper portion of the first insulating layer(22). The second insulating layer(28a) is formed on an upper portion of the blocking layer(26a). A contact hole is formed by etching continuously predetermined parts of the first insulating layer(22) and the blocking layer(28a). A metal barrier layer(30) is formed on the inside of the contact hole and the second insulating layer(28a). A metal layer(32) is formed by depositing a conductive material on the contact hole.

Abstract translation: 目的：提供一种用于形成半导体器件的导线的方法，以在形成电线的工艺中形成阻挡层来提高半导体的产量。 构成：包括第一导电图案（24）的第一绝缘层（22）形成在半导体衬底（20）上。 在第一绝缘层（22）的上部形成阻挡层（26a）。 第二绝缘层（28a）形成在阻挡层（26a）的上部。 通过连续蚀刻第一绝缘层（22）和阻挡层（28a）的预定部分形成接触孔。 在接触孔的内侧和第二绝缘层（28a）上形成金属阻挡层（30）。 通过在导电孔上沉积导电材料形成金属层（32）。

公开(公告)号：KR100335489B1

公开(公告)日：2002-05-04

申请号：KR1019990042033

申请日：1999-09-30

Applicant: 삼성전자주식회사

Inventor： 홍진기 ,  구주선

IPC: H01L21/28

Abstract: 본발명은라이너스페이서형성단계를구비하는콘택패드형성방법에대한것이다. 본발명의콘택패드형성방법에구비되는라이너스페이서형성단계는층간절연막내에콘택홀을형성하는단계와상기콘택홀에도전물질을채우는단계사이에구비된다. 상기라이너스페이서형성단계는소정두께의절연막을콘택홀내에형성한다음, 이방성식각을실시하여라이너스페이서를콘택홀의측벽에형성한다. 상기라이너스페이서는콘택패드간에발생될수 있는브릿지를예방하는기능을수행한다. 따라서, 상기라이너스페이서형성공정을콘택패드형성공정에제공함으로써, 반도체소자생산수율을향상시킬수 있다.

公开(公告)号：KR1020010029284A

公开(公告)日：2001-04-06

申请号：KR1019990042033

申请日：1999-09-30

Applicant: 삼성전자주식회사

Inventor： 홍진기 ,  구주선

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a contact pad is to prevent a bridge from being generated between adjacent contact pads. CONSTITUTION: The first interlayer dielectric layer(31) is formed on a conductive layer(30) of a semiconductor substrate. An interlayer interconnection(32) is formed on a predetermined region of the first interlayer dielectric layer. The second interlayer dielectric layer(33) is formed on the entire surface of the semiconductor substrate with the interlayer interconnection formed thereon. A void/seam(34) is formed between the interlayer interconnections. A contact hole is formed in the first and the second interlayer dielectric layer. An insulating layer is formed on the entire surface of the conductive layer with the contact hole formed therein. A liner spacer(36) is formed on the sidewall of the conductive layer by performing a dry etching process. A conductive material is filled in the contact hole after cleaning the conductive layer with the liner spacer formed on the sidewall thereof. A contact pad(40) is formed by planarizing the entire surface of the conductive layer with a conductive material.

Abstract translation: 目的：形成接触焊盘的方法是防止在相邻接触焊盘之间产生桥。 构成：第一层间介电层（31）形成在半导体衬底的导电层（30）上。 在第一层间电介质层的预定区域上形成层间布线（32）。 第二层间电介质层（33）形成在其上形成有层间连接的半导体衬底的整个表面上。 在层间互连之间形成空隙/接缝（34）。 在第一和第二层间电介质层中形成接触孔。 在形成有接触孔的导电层的整个表面上形成绝缘层。 通过进行干蚀刻工艺，在导电层的侧壁上形成衬垫（36）。 在形成在其侧壁上的衬垫衬垫清洁导电层之后，将导电材料填充在接触孔中。 通过用导电材料平坦化导电层的整个表面来形成接触焊盘（40）。

公开(公告)号：KR1020000013841A

公开(公告)日：2000-03-06

申请号：KR1019980032936

申请日：1998-08-13

Applicant: 삼성전자주식회사

Inventor： 김도형 ,  홍진기

IPC: H01L21/76

Abstract: PURPOSE: A manufacturing method of an isolation trench is provided to prevent a dent of a nitride liner caused by an over-etch of the nitride liner, the dent generated at an edge part of an upper region of the isolation trench. CONSTITUTION: The manufacturing method comprises the steps of: forming a mask pattern for defining the isolation trench region by partially etching a pad oxidation layer and a nitride layer; forming a trench by using the mask pattern to partially etch a part of a semiconductor substrate; forming a thermal oxidation layer on the bottom and sidewalls of the trench; forming a nitride liner on the thermal oxidation layer of which an etch rate is lower than that of the nitride layer of the mask pattern; filling up the trench with a trench isolation layer on the nitride liner; etching the trench isolation layer until an upper part of the mask pattern on both sides of the trench is exposed; and etching the mask pattern.

Abstract translation: 目的：提供隔离沟槽的制造方法，以防止在隔离沟槽的上部区域的边缘部分处产生的氮化物衬垫的过度蚀刻导致的氮化物衬垫凹陷。 构成：制造方法包括以下步骤：通过部分蚀刻焊盘氧化层和氮化物层，形成用于限定隔离沟槽区的掩模图案; 通过使用掩模图案来形成沟槽以部分蚀刻半导体衬底的一部分; 在沟槽的底部和侧壁上形成热氧化层; 在所述热氧化层上形成蚀刻速率低于所述掩模图案的氮化物层的蚀刻速率的氮化物衬垫; 在氮化物衬垫上用沟槽隔离层填充沟槽; 蚀刻沟槽隔离层，直到沟槽两侧的掩模图案的上部露出; 并蚀刻掩模图案。

公开(公告)号：KR1020000002488A

公开(公告)日：2000-01-15

申请号：KR1019980023275

申请日：1998-06-20

Applicant: 삼성전자주식회사

Inventor： 이주범 ,  홍진기

IPC: H01L21/302

Abstract: PURPOSE: A semiconductor device production method is provided to prevent a pin hole formed on the oxide film made on the a SOG group film. CONSTITUTION: The semiconductor device production method comprises steps of; evaporating the 1st oxide film on the 1st conductor formed on the wafer(34); spreading a SOG group film for a flattening on the 1st oxide film; evaporating the 2nd oxide film on the SOG group film(40) with a multiplex layer so that each layer of the 2nd oxide film may have specified thickness.

Abstract translation: 目的：提供一种半导体器件制造方法，以防止在SOG族膜上形成的氧化膜上形成的针孔。 构成：半导体器件制造方法包括以下步骤： 蒸发形成在晶片（34）上的第一导体上的第一氧化膜; 在第一氧化膜上铺展SOG组膜用于平坦化; 用多重层蒸发SOG基膜（40）上的第二氧化物膜，使得第二氧化物膜的每层可以具有规定的厚度。

公开(公告)号：KR1019990040443A

公开(公告)日：1999-06-05

申请号：KR1019970060818

申请日：1997-11-18

Applicant: 삼성전자주식회사

Inventor： 김주완 ,  홍진기 ,  김형수 ,  임영진 ,  이주범

IPC: H01L21/31

Abstract: 본 발명은 다단계로 미세한 선폭과 고 종횡비를 갖는 영역에 절연막을 채우는 반도체 장치의 제조 방법에 관해 개시한다. 최초 단계에서 상기 영역에 제1 절연막을 채우고 중간 단계에서 상기 제1 절연막의 전면을 식각하고, 최종 단계에서 상기 제1 절연막 상에 상기 영역을 완전히 채우는 제2 절연막을 형성한다. 상기 제1 절연막을 채우는 과정에서 상기 제1 절연막에 보이드가 형성되기도 하지만, 상기 중간 단계를 거치면서 상기 보이드는 제거되고 상기 제1 절연막의 표면은 상기 제2 절연막을 형성하기 적합한 상태가 된다. 따라서, 상기 제2 절연막을 채우는 과정에서 상기 영역에 보이드가 형성되지 않는다.

公开(公告)号：KR1019930008986A

公开(公告)日：1993-05-22

申请号：KR1019910017446

申请日：1991-10-04

Applicant: 삼성전자주식회사

Inventor： 홍진기 ,  김병준 ,  이정규 ,  이정기

IPC: H01L21/31

公开(公告)号：KR1020160028086A

公开(公告)日：2016-03-11

申请号：KR1020140116461

申请日：2014-09-02

Applicant: 삼성전자주식회사

Inventor： 최번재 ,  박영수 ,  류영호 ,  박태영 ,  홍진기

IPC: H01L33/36

CPC classification number: H01L33/382 ,  H01L33/405 ,  H01L33/42 ,  H01L33/62 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2924/00014

Abstract: 본발명의일 실시예는, 서로반대에위치한제1 및제2 면과그 사이의측면을가지며, 각각상기제1 및제2 면을제공하는제1 및제2 도전형반도체층과그 사이에위치한활성층을갖는반도체적층체와, 상기반도체적층체의제1 면에위치하며상기제1 도전형반도체층에접속된제1 전극과, 상기반도체적층체의제2 면에위치하며상기제2 도전형반도체층에접속된제2 전극과, 상기제2 전극에연결되어상기반도체적층체의제1 면까지연장된연결전극(connecting electrode)과, 상기제2 전극상에위치하는지지기판과, 상기연결전극과상기활성층및 상기제1 도전형반도체층사이에배치된절연막을포함하는반도체발광소자를제공한다.

Abstract translation: 本发明的实施例提供一种用于防止可靠性劣化的半导体发光器件。 半导体发光器件包括：具有彼此面对的第一表面和第二表面以及它们之间的侧表面的半导体层叠体，设置在第一表面和第二表面中的每个表面上的第一和第二导电类型半导体层，以及 位于它们之间的活性层; 第一电极，其位于半导体层叠体的第一表面上并连接到第一导电类型半导体层; 第二电极，其位于半导体层叠体的第二表面上并连接到第二导电类型半导体层; 连接电极，其连接到第二电极并延伸到半导体层叠体的第一表面; 位于所述第二电极上的支撑基板; 以及布置在连接电极，有源层和第一导电类型半导体层中的绝缘层。

公开(公告)号：KR1020140104295A

公开(公告)日：2014-08-28

申请号：KR1020130018307

申请日：2013-02-20

Applicant: 삼성전자주식회사

Inventor： 김재윤 ,  이승재 ,  손하영 ,  홍진기 ,  황성덕

IPC: H01L21/304 ,  H01L33/00

CPC classification number: H01L21/6836 ,  H01L33/0095 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2933/0041

Abstract: Provided is a method for grinding a substrate which comprises the steps of: preparing a substrate including a first main surface having a semiconductor layer thereon and a second main surface which is opposite to the first main surface; attaching a support film to the first main surface using a glue; curing the glue by applying energy to the glue; grinding the second main surface of the substrate to reduce the thickness of the substrate; and removing the support film from the first main surface by applying a force to the support film in a non-traverse direction.

Abstract translation: 提供了一种研磨基板的方法，包括以下步骤：制备包括其上具有半导体层的第一主表面和与第一主表面相对的第二主表面的基板; 使用胶将支撑膜附接到第一主表面; 通过向胶水施加能量来固化胶水; 研磨衬底的第二主表面以减小衬底的厚度; 并且通过在非横向方向上对所述支撑膜施加力而从所述第一主表面移除所述支撑膜。