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公开(公告)号：KR1020140080575A
公开(公告)日：2014-07-01
申请号：KR1020120144129
申请日：2012-12-12
Applicant: 한국전자통신연구원
CPC classification number: H01L23/66 , H01L23/49844 , H01L2223/6655 , H01L2224/48091 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
Abstract: A package is provided. The package includes a chip plate, a chip mounting plate which is arranged in one side of a ground plate and has an upper surface which is lower than the ground plate, a chip which is mounted on the chip mounting plate, a first input/output terminal which faces the chip mounting plate, is arranged in one side of the ground plate, and is electrically connected to the chip, and a second input/output terminal which faces the ground plate, is arranged in the other side of the chip mounting plate, and is electrically connected to the chip.
Abstract translation: 提供一个包装。 该封装包括芯片板，芯片安装板，其布置在接地板的一侧并具有比接地板低的上表面，安装在芯片安装板上的芯片，第一输入/输出 面向芯片安装板的端子布置在接地板的一侧，并且电连接到芯片，并且面对接地板的第二输入/输出端子布置在芯片安装板的另一侧 并且电连接到芯片。
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公开(公告)号：KR1020140079539A
公开(公告)日：2014-06-27
申请号：KR1020120146836
申请日：2012-12-14
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/66477 , H01L29/1608 , H01L29/2003 , H01L29/40 , H01L29/401 , H01L29/402 , H01L29/41 , H01L29/42312 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: The present invention relates to a transistor and a method of fabricating the same. A field effect transistor according to one embodiment of the present invention includes a source electrode and a drain electrode which are separated from each other on a substrate; and a + type gate electrode which is arranged on the substrate between the source electrode and the drain electrode. According to one embodiment of the present invention, the + type gate electrode includes a T type gate electrode part; and an additional gate electrode part.
Abstract translation: 晶体管及其制造方法技术领域本发明涉及晶体管及其制造方法。 根据本发明的一个实施例的场效应晶体管包括在基板上彼此分离的源电极和漏电极; 以及配置在源电极和漏电极之间的基板上的+型栅电极。 根据本发明的一个实施例，+型栅电极包括T型栅电极部分; 和附加的栅电极部分。
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公开(公告)号：KR1020130085224A
公开(公告)日：2013-07-29
申请号：KR1020120006224
申请日：2012-01-19
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: PURPOSE: A high electron mobility transistor and a manufacturing method thereof are provided to improve the stability of a T-type gate electrode by providing the high electron mobility transistor including an insulating film having a fine critical dimension. CONSTITUTION: A source electrode (202a) and a drain electrode (202b) are formed on a substrate (201). Insulating layers (203,206,208) including an opening part (209) between the source electrode and drain electrode are formed. The insulating layer comprises silicon nitride film or silicon oxide film. A T-type gate electrode (213) is formed at the upper part of the insulating layer. The body part of the T-type gate electrode is formed at the opening part of the insulating film.
Abstract translation: 目的：提供一种高电子迁移率晶体管及其制造方法，通过提供包括具有细小临界尺寸的绝缘膜的高电子迁移率晶体管来提高T型栅电极的稳定性。 构成：在基板（201）上形成源电极（202a）和漏电极（202b）。 形成包括源电极和漏电极之间的开口部分（209）的绝缘层（203,206,208）。 绝缘层包括氮化硅膜或氧化硅膜。 在绝缘层的上部形成T型栅电极（213）。 T型栅极的主体部分形成在绝缘膜的开口部分。
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公开(公告)号：KR1020130077432A
公开(公告)日：2013-07-09
申请号：KR1020110146139
申请日：2011-12-29
Applicant: 한국전자통신연구원
CPC classification number: H03G1/0082 , H03G1/0088 , H03G3/3084
Abstract: PURPOSE: An automatic gain control feedback amplifier is provided to freely control a gain even when a difference of an input signal is great. CONSTITUTION: An automatic gain control feedback amplifier (200) includes an amplifier circuit (210), a feedback circuit (220), and a bias circuit (230). The amplifier circuit amplifies a voltage inputted from an input terminal and outputs the voltage to an output terminal. The feedback circuit is connected between the input terminal and the output terminal. The feedback circuit includes a feedback resistor part (221) whose total voltage value is determined by one or more control signals and a feedback transistor connected to the feedback resistor part in parallel. The bias circuit provides a predetermined bias voltage to the feedback transistor.
Abstract translation: 目的：提供一种自动增益控制反馈放大器，即使当输入信号的差异大时也能自由地控制增益。 构成：自动增益控制反馈放大器（200）包括放大器电路（210），反馈电路（220）和偏置电路（230）。 放大器电路放大从输入端子输入的电压，并将该电压输出到输出端子。 反馈电路连接在输入端子和输出端子之间。 反馈电路包括其总电压值由一个或多个控制信号确定的反馈电阻器部分（221）和并联连接到反馈电阻器部分的反馈晶体管。 偏置电路向反馈晶体管提供预定的偏置电压。
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公开(公告)号：KR1020130069061A
公开(公告)日：2013-06-26
申请号：KR1020110136591
申请日：2011-12-16
Applicant: 한국전자통신연구원
CPC classification number: H04B10/90
Abstract: PURPOSE: A terahertz transmitter is provided to minimize signal loss. CONSTITUTION: An optical oscillator(110) generates optical signals having different correlation. A modulator(120) modulates the optical signals. A pre-amplifier(130) amplifies the modulated optical signals. An optical mixer(140) generates a terahertz signal by mixing the amplified optical signals. A post-amplifier(150) amplifies the terahertz signal. The post-amplifier transmits the amplified terahertz signal through an antenna. [Reference numerals] (110) Optical oscillator; (120) Modulator; (130) Pre-amplifier; (140) Optical mixer; (150) Post-amplifier
Abstract translation: 目的：提供太赫兹发射器以最小化信号损失。 构成：光学振荡器（110）产生具有不同相关性的光信号。 调制器（120）调制光信号。 前置放大器（130）放大经调制的光信号。 光混合器（140）通过混合放大的光信号产生太赫兹信号。 后置放大器（150）放大太赫兹信号。 后置放大器通过天线发射放大的太赫兹信号。 （110）光学振荡器; （120）调制器; （130）前置放大器; （140）光学混合器; （150）后置放大器
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Patent Agency Ranking
公开(公告)号：KR1020130059673A
公开(公告)日：2013-06-07
申请号：KR1020110125763
申请日：2011-11-29
Applicant: 한국전자통신연구원
IPC: H01L27/02 , H01L27/108 , H01L21/8242
CPC classification number: H01L28/91 , H01L23/481 , H01L28/92 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A vertical capacitor and a method for forming the same are provided to be manufactured in a substrate without a separate package. CONSTITUTION: An input electrode(14) and an output electrode(15) are formed in the upper surface(10a) of a substrate(10). A conductive material is formed in a first via hole formed by etching the lower surface(10b) of the substrate. The conductive material is connected to the input electrode and the output electrode. An input via electrode(24) and an output via electrode(25) are formed in the substrate. A dielectric layer(37) is formed between the input via electrode and the via electrode.
Abstract translation: 目的：提供垂直电容器及其形成方法，以便在基板上制造而不需要单独的封装。 构成：在基板（10）的上表面（10a）中形成有输入电极（14）和输出电极（15）。 在通过蚀刻基板的下表面（10b）形成的第一通孔中形成导电材料。 导电材料连接到输入电极和输出电极。 在基板中形成有输入通孔电极（24）和输出通孔电极（25）。 在输入通孔电极和通孔电极之间形成介电层（37）。
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公开(公告)号：KR101208035B1
公开(公告)日：2012-12-05
申请号：KR1020090028546
申请日：2009-04-02
Applicant: 한국전자통신연구원
Abstract: 본발명의실시예에따른전력증폭기의바이어스회로는기준전압을입력받는제 1 입력단, 바이어스제어전압을입력받는제 2 입력단, 상기제 1 입력단과제 1 노드사이에연결된바이어스저항, 상기제 2 입력단과제 2 노드사이에연결되며, 제 1 노드에응답하여전류통로를형성하는제 1 트랜지스터, 상기제 1 노드와제 3 노드사이에연결되며, 상기제 2 노드에응답하여전류통로를형성하는제 2 트랜지스터및 상기제 1 노드와출력단사이에연결되며, 상기출력단을통해바이어스전류를출력하기위한제 3 트랜지스터를포함한다.
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公开(公告)号：KR1020110067929A
公开(公告)日：2011-06-22
申请号：KR1020090124720
申请日：2009-12-15
Applicant: 한국전자통신연구원
CPC classification number: H01F17/0006 , H01F2017/0086 , H01L28/10
Abstract: PURPOSE: An inductor is provided to be mounted on a semiconductor substrate with a small area by using first to fourth vertical conductive units. CONSTITUTION: A first conductive line is electrically connected to a second conductive terminal(140b) and a third conductive terminal(140c). A second conductive line is electrically connected to a first conductive terminal(140a) and a fourth conductive terminal(140d). A third conductive line is electrically connected to the first conductive terminal and the third conductive terminal.
Abstract translation: 目的：通过使用第一至第四垂直导电单元，提供以小面积安装在半导体衬底上的电感器。 构成：第一导电线电连接到第二导电端子（140b）和第三导电端子（140c）。 第二导电线电连接到第一导电端子（140a）和第四导电端子（140d）。 第三导线与第一导电端子和第三导电端子电连接。
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公开(公告)号：KR1020100064588A
公开(公告)日：2010-06-15
申请号：KR1020080123093
申请日：2008-12-05
Applicant: 한국전자통신연구원
CPC classification number: H01L29/7304 , H01L29/66272 , H01L29/732
Abstract: PURPOSE: A compound semiconductor bipolar transistor and a forming method thereof are provided to improve the stability of a device by directly forming a capacitor on a base layer not the outside of the device. CONSTITUTION: A collector layer(112) is arranged on a substrate. A base layer is arranged on the collector layer. An emitter layer is formed on the base layer and covers a part of the base layer. A bottom electrode(122a) is contacted with the base layer. A pair of resistance electrodes are arranged on the base layer. A dielectric layer covers the bottom electrode. A top electrode(150) faces the bottom electrode and is arranged on the dielectric layer.
Abstract translation: 目的：提供一种化合物半导体双极晶体管及其形成方法，以通过在基底层而不是设备外部直接形成电容器来提高器件的稳定性。 构成：集电极层（112）布置在基板上。 基层设置在集电极层上。 发射极层形成在基底层上并覆盖基底层的一部分。 底部电极（122a）与基底层接触。 一对电阻电极布置在基层上。 电介质层覆盖底部电极。 顶部电极（150）面向底部电极并布置在电介质层上。
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公开(公告)号：KR1020100061608A
公开(公告)日：2010-06-08
申请号：KR1020080120193
申请日：2008-11-29
Applicant: 한국전자통신연구원
IPC: H01L29/737 , H01L29/73
CPC classification number: H01L29/42304 , H01L29/41708 , H01L29/66318 , H01L29/7371
Abstract: PURPOSE: A heterogeneity laminating bipolar transistor and a formation method thereof are provided to reduce a parasitic capacitance by forming an electrode wiring of an emitter electrode, a base electrode and a collector electrode into an air bridge form using the plating process. CONSTITUTION: A sub-collector pattern(110), a base pattern(120), an emitter pattern(132) and an emitter capping pattern(134) are formed on a substrate. An emitter electrode(136) is formed on the emitter capping pattern. A base electrode(122) is formed on the base pattern. A collector electrode(114) is formed on the sub-collector pattern. The emitter electrode, the base electrode and the collector electrode are exposed by patterning a first dummy pattern. A plating seed layer is formed on the exposed emitter electrode, the base electrode and the collector electrode.
Abstract translation: 目的：提供异质层压双极晶体管及其形成方法，以通过使用电镀工艺将发射电极，基极和集电极的电极布线形成为气桥形式来减小寄生电容。 构成：在基板上形成亚集电体图案（110），基底图案（120），发射极图案（132）和发射极封盖图案（134）。 在发射极盖图案上形成发射电极（136）。 在基底图案上形成基极（122）。 在集电极图案上形成集电极（114）。 通过图案化第一虚拟图案来暴露发射极，基极和集电极。 在暴露的发射极，基极和集电极上形成电镀种子层。
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