公开(公告)号：MY123248A

公开(公告)日：2006-05-31

申请号：MYPI9904527

申请日：1999-10-20

Applicant: IBM

Inventor： BARTH JOHN E JR ,  BERTIN CLAUDE L ,  DREIBELBIS JEFFREY H ,  ELLIS WAYNE F ,  HOWELL WAYNE J ,  HEDBERG ERIK L ,  KALTER HOWARD LEO ,  TONTI WILLIAM R ,  WHEATER DONALD L

IPC: G11C29/00 ,  H01L21/66 ,  G01R31/28 ,  G01R31/319

Abstract: WAFER TEST AND BURN-IN IS ACCOMPLISHED WITH STATE MACHINE OR PROGRAMMABLE TEST ENGINES (29) LOCATED ON THE WAFER (26) BEING TESTED. EACH TEST ENGINE REQUIRE LESS THAN 10 CONNECTIONS AND EACH TEST ENGINE CAN BE CONNECTED TO A PLURALITY OF CHIPS (28-28", 28A-28E), SUCH AS A ROW OR A COLUMN OF CHIPS ON THE WAFER. THUS, THE NUMBER OF PADS (1-8) OF THE WAFER THAT MUST BE CONNECTED FOR TEST IS SUBSTANTIALLY REDUCED WHILE A LARGE DEGREE OF PARALLEL TESTING IS STILL PROVIDED. THE TEST ENGINES ALSO PERMIT ON-WAFER ALLOCATION OF REDUNDANCY IN PARALLEL SO THAT FAILING CHIPS CAN BE REPAIRED AFTER BURN-IN COMPLETE. IN ADDITION, THE PROGRAMMABLE TEST ENGINES CAN HAVE THEIR CODE ALTERED SO TEST PROGRAMS CAN BE MODIFIED TO ACCOUNT FOR NEW INFORMATION AFTER THE WAFER HAS BEEN FABRICATED. THE TEST ENGINES ARE USED DURING BURN-IN TO PROVIDE HIGH FREQUENCY WRITE SIGNALS TO DRAM ARRAYS THAT PROVIDE A HIGHER EFFECTIVE VOLTAGE TO THE ARRAYS, LOWERING THE TIME REQUIRED FOR BURN-IN. CONNECTIONS TO THE WAFER AND BETWEEN TEST ENGINES AND CHIPS ARE PROVIDED ALONG A MEMBERANE (20-20') ATTACHED TO THE WAFER. MEMBRANE CONNECTORS (31-31") CAN BE FORMED OR OPENED AFTER THE MEMBRANE IS CONNECTED TO THE WAFER SO SHORTED CHIPS CAN BE DISCONNECTED.PREFERABLY THE MEMBRANE REMAINS ON THE WAFER AFTER TEST, BURN-IN AND DICING TO PROVIDE A CHIP SCALE PACKAGE. THUS, THE VERY HIGH COST OF TCE MATCHED MATERIALS, SUCH AS GALSS CERAMIC CONTATCTORS, FOR WAFER BURN-IN IS AVOIDED WHILE PROVIDING BENEFIT BEYOND TEST AND BURN-IN FOR PACKAGING. (FIG. 2)

公开(公告)号：CA2118994A1

公开(公告)日：1994-12-22

申请号：CA2118994

申请日：1994-03-14

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  FARRAR PAUL A SR ,  HOWELL WAYNE J ,  MILLER CHRISTOPHER P ,  PERLMAN DAVID J

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L27/02 ,  H01L23/50 ,  H01L21/82

Abstract: POLYIMIDE-INSULATED CUBE PACKAGE OF STACKED SEMICONDUCTOR DEVICE CHIPS A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

公开(公告)号：DE3483863D1

公开(公告)日：1991-02-07

申请号：DE3483863

申请日：1984-08-10

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  KALTER HOWARD L

IPC: G11C17/08 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L29/78 ,  H01L21/82

Abstract: @ A read only memory (ROM) array of stacked IGFET devices composed of first and second sub-arrays of field effect transistors. The first sub-array of first field effect transistors is formed in a substrate. Each of the first field effect transistor devices is responsive to a polysilicon gate electrode. The second sub-array of second field effect transistors is formed in a layer of laser annealed polysilicon material which overlies the first sub-array. The gate electrodes of the first field effect transistors act as the gate electrodes of the second field effect transistors.

公开(公告)号：FR2289051A1

公开(公告)日：1976-05-21

申请号：FR7526335

申请日：1975-08-19

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  MONEDA FRANCISCO H DE LA

IPC: H03F1/52 ,  H01L21/265 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/06 ,  H01L29/78 ,  H02H7/20 ,  H03F1/42 ,  H03K17/0812 ,  H02H9/04

Abstract: Protective devices and circuits for insulated gate transistors are improved by another p/n junction diode or MOS diode preventing breakdown of the thin oxide of the protective device. The breakdown voltage of the protective device or p/n diode may be tailored to a preselected voltage by altering its metallurgical junction by ion implantation or other techniques. Tailoring permits the breakdown voltage of the protective device to be independent of process and circuit specification of a protected or internal circuit. A plurality of parallel circuits connected as a protective device limits or controls secondary breakdown of the protective device.

公开(公告)号：DE2544438A1

公开(公告)日：1976-04-29

申请号：DE2544438

申请日：1975-10-04

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  MONEDA FRANCISCO H DE LA

IPC: H03F1/52 ,  H01L21/265 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/06 ,  H01L29/78 ,  H02H7/20 ,  H03F1/42 ,  H03K17/0812

Abstract: Protective devices and circuits for insulated gate transistors are improved by another p/n junction diode or MOS diode preventing breakdown of the thin oxide of the protective device. The breakdown voltage of the protective device or p/n diode may be tailored to a preselected voltage by altering its metallurgical junction by ion implantation or other techniques. Tailoring permits the breakdown voltage of the protective device to be independent of process and circuit specification of a protected or internal circuit. A plurality of parallel circuits connected as a protective device limits or controls secondary breakdown of the protective device.

公开(公告)号：MY134452A

公开(公告)日：2007-12-31

申请号：MYPI20054051

申请日：2001-05-23

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  DIVAKARUNI RAMACHANDRA ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/00 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: AN ANTI-FUSE STRUCTURE THAT CAN BE PROGRAMMED AT LOW VOLTAGE AND CURRENT AND WHICH POTENTIALLY CONSUMES VERY LITTLE CHIP SPACES AND CAN BE FORMED INTERSTITIALLY BETWEEN ELEMENTS SPACED BY A MINIMUM LITHOGRAPHIC FEATURE SIZE IS FORMED ON A COMPOSITE SUBSTRATE SUCH AS A SILICON-ONINSULATOR WAFER BY ETCHING A CONTACT THROUGH AN INSULATOR TO A SUPPORT SEMICONDUCTOR LAYER, PREFERABLY IN COMBINATION WITH FORMATION OF A CAPACITOR-LIKE STRUCTURE REACHING TO OR INTO THE SUPPORT LAYER. THE ANTI-FUSE MAY BE PROGRAMMED EITHER BY THE SELECTED LOCATION OF CONDUCTOR FORMATION AND/OR DAMAGING A DIELECTRIC OF THE CAPACITOR-LIKE STRUCTURE. AN INSULATING COLLAR (38, 90) IS USED TO SURROUND A PORTION OF EITHER THE CONDUCTOR (42, 100) OR THE CAPACITOR-LIKE STRUCTURE TO CONFINE DAMAGE TO THE DESIRED LOCATION.HEATING EFFECTS VOLTAGE AND NOISE DUE TO PROGRAMMING CURRENTS ARE EFFECTIVELY ISOLATED TO THE BULK SILICON LAYER, PERMITTING PROGRAMMING DURING NORMAL OPERATION OF THE DEVICE. THUS THE POTENTIAL FOR SELF-REPAIR WITHOUT INTERRUPTION OF OPERATION IS REALIZED.(FIG 6)

公开(公告)号：IT1165312B

公开(公告)日：1987-04-22

申请号：IT2585279

申请日：1979-09-20

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  BULA JOHN ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

IPC: G11C17/12 ,  H01L23/525 ,  G11C17/00 ,  G11C

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

公开(公告)号：DE3067978D1

公开(公告)日：1984-06-28

申请号：DE3067978

申请日：1980-12-16

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  DE LA MONEDA FRANCISCO H ,  SODERMAN DONALD A

IPC: H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

Abstract: A diffused MOS (DMOS) device and method for making same are disclosed. The prior art DMOS device is improved upon by ion implanting a depletion extension LD to the drain. However, the introduction of the depletion extension LD introduces a manufacturing statistical variation in the characteristics of the resultant devices so produced. The problem of the effects of the variations in the length LD+L, and thus, variations in the resulting transconductance of the device, is solved by placing two of these devices in parallel. When one device has its LD relatively shorter, the companion device will also have its LD correspondingly longer. The method of producing the dual devices is by ion implanting a single conductivity region which forms the LD for both the left- and right-hand channels for the left- and right-hand DMOS structures. If the mask for the ion-implanted region is misaligned slightly to the right, then the effective LD for the right-hand channel is somewhat longer but the effective LD for the left-hand channel is correspondingly shorter, so that the net parallel transconductance for the two devices remains the same as the transconductance for a perfectly symmetric ion-implanted region.

公开(公告)号：DE2965440D1

公开(公告)日：1983-07-07

申请号：DE2965440

申请日：1979-08-23

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  BULA JOHN ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

IPC: G11C17/00 ,  G11C17/12 ,  H01L23/525

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.