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    Method for forming porous organic dielectric layer
    12.
    发明专利
    Method for forming porous organic dielectric layer 有权
    用于形成多孔有机电介质层的方法

    公开(公告)号：JP2004336051A

    公开(公告)日：2004-11-25

    申请号：JP2004136335

    申请日：2004-04-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CLEVENGER LAWRENCE A ,  GRECO STEPHEN E ,  KWIETNIAK KEITH T ,  SEO SOON-CHEON ,  YANG CHIH-CHAO ,  WANG YUN-YU ,  WONG KWONG H

    IPC: H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

    CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a wiring layer in an integrated circuit structure.
    SOLUTION: An organic insulating layer is formed, the insulating layer is patterned, a liner is accumulated on the insulating layer, the above structure is exposed in plasma, and a pore is formed in an insulating layer of an area adjacent to the liner. The liner is formed sufficiently thin so that plasma penetrates the liner and the pore is formed on the insulating layer without influencing the liner. During the plasma processing, the plasma penetrates the liner without influencing the liner. After the plasma processing, an additional liner can be accumulated. Thereafter, a conductor is accumulated and an excessive portion of the conductor is deleted from the structure. This method produces an integrated circuit structure including the organic insulating layer having a patterned structure, a liner covering the rear side of the patterned structure, and a conductor filling the patterned structure. The insulating layer includes the pore along the surface area of the insulating layer contacting to the liner, and further, the pore is only existent along the surface area contacting to the liner (where the liner is non-existent inside the pore).
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于在集成电路结构中形成布线层的方法。 解决方案：形成有机绝缘层，对绝缘层进行图案化，在绝缘层上积累衬垫，将上述结构暴露在等离子体中，并且在邻近的区域的绝缘层中形成孔 衬垫。 衬垫形成得足够薄，使得等离子体穿透衬垫，并且在绝缘层上形成孔而不影响衬垫。 在等离子体处理期间，等离子体渗透衬垫而不影响衬套。 在等离子体处理之后，可以累积额外的衬垫。 此后，导体被累积，导体的过多部分从结构中删除。 该方法产生包括具有图案化结构的有机绝缘层，覆盖图案化结构的后侧的衬垫和填充图案化结构的导体的集成电路结构。 绝缘层包括沿着与衬垫接触的绝缘层的表面积的孔，此外，孔沿着与衬垫接触的表面区域（其中衬里不存在于孔内）存在。 版权所有（C）2005，JPO＆NCIPI

    THIN FILM TRANSISTOR DEVICE, AND THEIR FORMING METHOD
    13.
    发明专利
    THIN FILM TRANSISTOR DEVICE, AND THEIR FORMING METHOD 审中-公开

    公开(公告)号：JP2003229435A

    公开(公告)日：2003-08-15

    申请号：JP2003003523

    申请日：2003-01-09

    Applicant: IBM

    Inventor： TORISHIA L BREEN ,  CLEVENGER LAWRENCE A ,  LEWIS L SUU ,  WANG LI-KONG ,  WONG KWONG HON

    IPC: H01L51/05 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786 ,  H01L35/24 ,  H01L51/00 ,  H01L51/40

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a flattened polymer transistor, and a structure thereof. SOLUTION: A completely flattened polymer thin film transistor is formed by processing a first portion of a device including a gate, a source, and a body element using a first flattened carrier. The thin film transistor is preferably formed with an organic material. For a gate dielectric a high K polymer can be employed to improve device performance. Then, a partly completed device structure is upside down, and is transferred to a second flattened carrier. A layer of wax or of a photosensitive organic material is deposited and is employed as a tentative bonding agent. A device including a body region is defined with an etching process. A contact to the device is formed with deposition of a conductive material and chemical/mechanical polishing. COPYRIGHT: (C)2003,JPO

    METHOD FOR PLANARIZING SEMICONDUCTOR DEVICE
    14.
    发明专利
    METHOD FOR PLANARIZING SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JP2002076003A

    公开(公告)日：2002-03-15

    申请号：JP2001171139

    申请日：2001-06-06

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS L C ,  STEPHENS JEREMY K ,  WISE MICHAEL

    IPC: H01L21/76 ,  H01L21/285 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a topography extremely reduced on a semiconductor surface formed by a damascene process. SOLUTION: A diamond or diamond like carbon film is adhered to the surface of a substrate as a polishing stop layer before a metal level pattern is formed. Next, a protective film is adhered on the diamond or diamond like carbon polishing stop layer. The protective film can be used as another polishing stop layer. Both the diamond or diamond like carbon film and the protective film are used as a hard mask so that a pattern is formed in a trench that has metallic features. The protective film protects the diamond or diamond like carbon polishing stop layer during a pattern forming process. After a conductive metal layer is adhered, the substrate is polished, and redundant conducting materials and the topography are removed.

    High permittivity material forming component of dram storage cell
    16.
    发明专利
    High permittivity material forming component of dram storage cell 有权
    高容量材料形成DRAM存储单元的组件

    公开(公告)号：JP2003037188A

    公开(公告)日：2003-02-07

    申请号：JP2002142692

    申请日：2002-05-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  SHEPARD JR JOSEPH F

    IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L27/1085 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/55

    Abstract: PROBLEM TO BE SOLVED: To provide a method, as well as structure, for manufacturing a dynamic random access memory device and a related transistor at the same time.
    SOLUTION: A channel region and a capacitor opening are formed in a substrate by this method. Then a capacitor conductor is allowed to stick to the capacitor opening. A single insulator layer is formed above the channel region and the capacitor conductor at the same time. The single insulator layer contains a capacitor node dielectrics above the capacitor conductor while a gate dielectrics above the channel region. A single conductor layer is patterned above the single insulator layer at the same time. The single conductor layer contains a gate conductor above the gate dielectrics while a ground plate above the capacitor node dielectrics.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供用于同时制造动态随机存取存储器件和相关晶体管的方法以及结构。 解决方案：通过该方法在衬底中形成沟道区和电容器开口。 然后允许电容器导体粘附到电容器开口。 在通道区域和电容器导体上同时形成单个绝缘体层。 单个绝缘体层在电容器导体上方包含电容器节点电介质，而沟道区域之上的栅极电介质。 单个导体层同时在单个绝缘体层上形成图案。 单导体层包含位于栅极电介质上方的栅极导体，而电容器节点电介质上方的接地板。

    METHOD OF MANUFACTURING POLYMER CONDUCTING WIRE AND INTEGRATED CIRCUIT STRUCTURE
    17.
    发明专利
    METHOD OF MANUFACTURING POLYMER CONDUCTING WIRE AND INTEGRATED CIRCUIT STRUCTURE 审中-公开

    公开(公告)号：JP2003133317A

    公开(公告)日：2003-05-09

    申请号：JP2002193642

    申请日：2002-07-02

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  WANG LI-KONG ,  WONG KEITH KWONG HON

    IPC: G03F7/40 ,  H01B13/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H05K3/02

    Abstract: PROBLEM TO BE SOLVED: To provide a more simplified substitutional method of the conventional damascene approach. SOLUTION: The cloisonne approach includes a step of coating a semiconductor substrate with a photosensitive polymer, such as pyrrole having a silver salt, aniline, etc. A conductive polymer is exposed to a wet developing solution, by using standard photolithography and the resists developing method and only conductive polymer wires are left on a substrate by removing part of the exposed conductive polymer region. Then an insulating dielectric layer is adhered to the whole structure, and conductive polymer wires are produced by planarizing an insulator by the chemical mechanical polishing (CMP). Another embodiment of this invention includes a method and structure for a self- planarizing interconnecting material containing the conductive polymer. Consequently, the number of treating steps can be reduced, as compared with the conventional technology.

    INTEGRATED CIRCUIT CHIP STRUCTURE AND MANUFACTURING METHOD THEREOF
    19.
    发明专利
    INTEGRATED CIRCUIT CHIP STRUCTURE AND MANUFACTURING METHOD THEREOF 失效

    公开(公告)号：JP2001102453A

    公开(公告)日：2001-04-13

    申请号：JP2000245862

    申请日：2000-08-14

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHU

    IPC: H01L23/522 ,  H01L21/314 ,  H01L21/764 ,  H01L21/768 ,  H01L23/482 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide a structure and a process for incorporating air or another gas in a multi-layer chip as a permanent dielectric medium by supplying a CVD diamond as dielectrics in semi-sacrificial layer and in-layer dielectrics. SOLUTION: A CVD diamond is supplied as dielectrics in semi-sacrificial layer and in-layer dielectrics, and then a semi-sacrificial dielectrics is at least partially removed by isotropic oxygen etching. A disclosed one deformed example presents a eventual permanent CVD diamond sealing material for a gas dielectric medium to be confined in a chip.

    INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME
    20.
    发明申请
    INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME 审中-公开
    互连结构及其制造方法

    公开(公告)号：WO2006113186A3

    公开(公告)日：2008-07-24

    申请号：PCT/US2006013179

    申请日：2006-04-07

    Applicant: IBM ,  YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

    Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

    IPC: H01L21/4763

    CPC classification number: H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

    Abstract translation: 一种镶嵌线及其形成方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。 该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

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