公开(公告)号：EP1869700A4

公开(公告)日：2010-12-15

申请号：EP06740771

申请日：2006-04-07

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1836726A4

公开(公告)日：2010-07-28

申请号：EP05852629

申请日：2005-12-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL J ,  STANDAERT THEODORUS E ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L21/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2004193605A

公开(公告)日：2004-07-08

申请号：JP2003405153

申请日：2003-12-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DALTON TIMOTHY J ,  DAS SANJIT K ,  ENGEL BRETT H ,  HERBST BRIAN W ,  HICHRI HABIB ,  KASTENMEIER BERND E ,  MALONE KELLY ,  MARINO JEFFREY R ,  MARTIN ARTHUR ,  MCGAHAY VINCENT J ,  MELVILLE IAN D ,  NARAYAN CHANDRASEKHAR ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for reducing thermal mechanical stress in stack and via. SOLUTION: An interconnection structure for a semiconductor device comprises an organic low-k (low specific dielectric constant) dielectric layer formed on a lower metallization. The via to be formed here is in this low-k dielectric layer, and combines a lower metallization line formed on the lower metallization level and an upper metallization line formed on an upper metallization level. This via is surrounded by structure collar selected from material with CTE that can protect the via from shearing force generated after the thermal expansion of the low-k dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2001351976A

公开(公告)日：2001-12-21

申请号：JP2001117668

申请日：2001-04-17

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  CHRISTOPHER V JARNES ,  JOYCE C RYUU ,  PURUSHOTHAMAN SAMPATH

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a permanent protection hard mask for protecting the dielectric characteristics of a main dielectric layer that has undesired low permittivity of a semiconductor device due to undesired increase in permittivity, undesired increase in current leakage, and a low device yield caused by surface scratch, when a continuous treatment processing is conducted. SOLUTION: This protection hard mask has a one- or two-layer sacrificial hard mask that is especially effective, when interconnection structure such as a via opening and/or a line is formed between low-permittivity materials, while a final product is manufacture. The sacrificial and permanent hard masks are formed of the same precursor substance in a single process, where process conditions are changed for giving a film having different permittivity. Most preferably, dual damascene structure has three-layer hard masks 40, 50, and 60 that are formed on the inter-level dielectric with bulk low permittivity, before the interconnection structure of the inter-level dielectric is formed.

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005094014A

公开(公告)日：2005-04-07

申请号：JP2004269168

申请日：2004-09-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DALTON TIMOTHY J ,  GATES STEPHEN M

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/02063 ,  H01L21/76814

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a BEOL interconnection structure provided with a plurality of via contacts each having low via-contact resistance on a semiconductor device. SOLUTION: The method includes steps of: forming a porous or dense low-k dielectric layer on a substrate; forming, in the low-k dielectric layer, an opening etched by means of a single or dual damascene process; arranging the substrate on a cold chuck at a temperature of about -200°C to about 25°C inside a process chamber; additively introducing a condensable cleaning agent into the process chamber to have a CCA layer condensed inside the etched opening on the substrate; and implementing an activation step while a wafer is cooled down to a temperature of about -200°C to about 25°C. This via contact is extremely stable during a temperature cycle and the operation of the semiconductor device. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造具有在半导体器件上具有低通孔接触电阻的多个通孔触点的BEOL互连结构的方法。 解决方案：该方法包括以下步骤：在衬底上形成多孔或致密的低k电介质层; 在低k电介质层中形成通过单镶嵌或双镶嵌工艺蚀刻的开口; 将衬底在处理室内的约-200℃至约25℃的温度下布置在冷卡盘上; 将可冷凝清洁剂加入到处理室中以使CCA层在衬底上的蚀刻开口内冷凝; 并且在将晶片冷却至约-200℃至约25℃的温度的同时实施激活步骤。 该通孔接触在温度循环和半导体器件的操作期间非常稳定。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004146800A

公开(公告)日：2004-05-20

申请号：JP2003313299

申请日：2003-09-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CANAPERI DONALD F ,  DALTON TIMOTHY J ,  GATES STEPHEN M ,  KRISHNAN MAHADEVAIYER ,  PURUSHOTHAMAN SAMPATH ,  SMITH SEAN P E ,  NITTA SATYA

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure which realizes high performance interconnection including copper wiring and an insulator having an extremely low dielectric constant (k). SOLUTION: In this structure, wiring is supported by a low-k dielectric material having relatively high durability, such as SiLk(R) or SiO 2 , and then the remaining spaces in the structure are filled with a gap filling dielectric material that has an extremely low-k and a small hardness. Accordingly, in the structure, durable layers for obtaining the strength are bonded with an extremely low-k dielectric material for achieving electric performance of the interconnection. As a result, damages to and an increase in dielectric constant of the extremely low-k dielectric material caused during the manufacturing process are avoided, and delamination in the structure during the metal chemical mechanical polishing processes is prevented. Further, photoresist poisoning troubles caused by interaction with the extremely low-k dielectric material can be removed. COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2009100053A2

公开(公告)日：2009-08-13

申请号：PCT/US2009032936

申请日：2009-02-03

Applicant: IBM ,  BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

Inventor： BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

IPC: H01L21/20

CPC classification number: H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

Abstract: In one embodiment, hexagonal tiles encompassing a large are divided into three groups, each containing one-third of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group (01, 02, 03) are formed in a template layer (2OA, 2OB, 20C), and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self- aligned line and space structures (4OA, 5OA; 4OB, 5OB; 4OC, 50C) are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

Abstract translation: 在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的三分之一。 每个组（01,02,03）中的六边形瓦片的开口形成在模板层（20A，20B，20C）中，并且在每个开口内施加和组合一组自组装嵌段共聚物。 该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。 在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。 每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。 在每组中以顺序的方式形成自组装自对准线和空间结构（40A，50A; 40B，50B; 40C，50C），使得线和空间图形形成在延伸超过 订购。

公开(公告)号：WO2007016047A3

公开(公告)日：2008-01-03

申请号：PCT/US2006028718

申请日：2006-07-24

Applicant: IBM ,  GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

Inventor： GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: B82Y10/00 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

Abstract translation: 磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。 上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

公开(公告)号：WO2006113186A3

公开(公告)日：2008-07-24

申请号：PCT/US2006013179

申请日：2006-04-07

Applicant: IBM ,  YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

Abstract translation: 一种镶嵌线及其形成方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。 该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。