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    SEMICONDUCTOR BODY, DYNAMIC RANDOM ACCESS MEMORY, ELECTRIC ISOLATION, AND MANUFACTURE OF MEMORY CELL
    13.
    发明专利
    SEMICONDUCTOR BODY, DYNAMIC RANDOM ACCESS MEMORY, ELECTRIC ISOLATION, AND MANUFACTURE OF MEMORY CELL 失效

    公开(公告)号：JP2000228504A

    公开(公告)日：2000-08-15

    申请号：JP2000028340

    申请日：2000-02-04

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： MANDELMAN JACK A ,  LAROSA GIUSEPPE ,  RADENS CARL ,  DIVAKARUNI RAMA ,  GRUENING ULRIKE

    IPC: H01L21/76 ,  H01L21/763 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a dynamic random access memory formed at a semiconductor body comprising individual paired memory cell separated each other by a vertical electric isolation trench and separated from a support circuit. SOLUTION: An isolation trench 20, comprising a side wall, upper part, and lower part, encloses the region of a semiconductor body 10 comprising a memory cell. Thus, the paired memory cell is electrically separated each other, while separated from a support circuit which is not in the enclosed region but contained in the semiconductor body. The isolation trench lower-part is filled with a conductive material 14, which material comprises a side wall part which is at least partially separated from the trench lower-part side wall by a first electric insulator and a lower part electrically connecting to the semiconductor body. The isolation trench upper-part is filled with a second electric insulator.

    15.
    发明专利
    未知

    公开(公告)号：DE10215666A1

    公开(公告)日：2002-11-07

    申请号：DE10215666

    申请日：2002-04-09

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DYER THOMAS ,  MALIK RAIEEV ,  DIVAKARUNI RAMA ,  MANDELMAN JACK A ,  JAIPRAKASH V C

    IPC: H01L21/316 ,  H01L21/318 ,  H01L21/8242

    Abstract: A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

    17.
    发明专利
    未知

    公开(公告)号：AT519228T

    公开(公告)日：2011-08-15

    申请号：AT00103964

    申请日：2000-02-25

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.

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