13.
    发明专利
    未知

    公开(公告)号:DE69737469D1

    公开(公告)日:2007-04-26

    申请号:DE69737469

    申请日:1997-04-24

    Applicant: SIEMENS AG IBM

    Abstract: According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.

    14.
    发明专利
    未知

    公开(公告)号:DE69534699T2

    公开(公告)日:2006-07-20

    申请号:DE69534699

    申请日:1995-09-22

    Applicant: IBM

    Abstract: Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element. In particular, comparison between traces of undoped oxide and fluorosilicate glass clearly shows that the former has a greater SIOH concentration which is a manufacturing yield detractor.

    15.
    发明专利
    未知

    公开(公告)号:DE69618548T2

    公开(公告)日:2002-09-12

    申请号:DE69618548

    申请日:1996-10-24

    Applicant: IBM

    Abstract: A method of forming interlevel studs in an insulating layer on a semiconductor wafer. First, a conformal BPSG layer is formed on a Front End of the Line (FEOL) semiconductor structure. Vias are opened through the BPSG layer to the FEOL structure. A layer of poly is formed (deposited) on the BPSG layer, filling the vias. The poly layer may be insitu doped poly or implanted after it is deposited. The wafer is annealed to diffuse dopant from the poly to form diffusions wherever the poly contacts the substrate. A non-selective slurry of colloidal silica and at least 1% ammonium hydroxide is used to chem-mech polish the poly from the BPSG layer and, simultaneously, planarize the BPSG layer.

Patent Agency Ranking