公开(公告)号：GB2493238B

公开(公告)日：2014-04-16

申请号：GB201208558

申请日：2011-04-26

Applicant: IBM

Inventor： CHEN KUAN-NENG ,  LIN YU-MING ,  AVOURIS PHAEDON ,  FARMER DAMON BROOKS

IPC: H01L21/822 ,  B82Y10/00 ,  H01L27/06 ,  H01L27/12 ,  H01L29/16 ,  H01L29/786

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

公开(公告)号：GB2499311A

公开(公告)日：2013-08-14

申请号：GB201300509

申请日：2013-01-11

Applicant: IBM

Inventor： DIMITRAKOPOULOS CHRISTOS ,  GRILL ALFRED ,  NEUMAYER DEBORAH ANN ,  PFEIFFER DIRK ,  ZHU WENJUAN ,  FARMER DAMON BROOKS ,  LIN YU-MING

IPC: H01L29/786 ,  B82Y40/00 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66

Abstract: A silicon nitride layer 16 is provided on an uppermost surface of a graphene layer 14 and then a hafnium dioxide layer 18 is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer. The graphene layer can be epitaxially grown on a substrate which may be silicon carbide. The silicon nitride layer may be a tensile silicon nitride layer. A portion of the graphene layer may serve as a channel layer for a FET. The graphene layer may be in contact with source and drain regions of an FET 56, 58. A gate conductor 54 may be located on the hafnium oxide layer. The dielectric bilayer may cover the sides and the top of the source drain regions.

公开(公告)号：GB2497248A

公开(公告)日：2013-06-05

申请号：GB201305445

申请日：2011-07-20

Applicant: IBM

Inventor： AVOURIS PHAEDON ,  FARMER DAMON BROOKS ,  LIN YU-MING ,  ZHU YU

IPC: H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

Abstract: A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.

公开(公告)号：DE112018001069T5

公开(公告)日：2019-11-21

申请号：DE112018001069

申请日：2018-05-17

Applicant: IBM

Inventor： FARMER DAMON BROOKS ,  TANG JIANSHI ,  YURKAS JOHN JACOB ,  HAN SHU-JEN

IPC: H01L29/772

Abstract: Ausführungsformen der vorliegenden Erfindung beziehen sich auf Verfahren und resultierende Strukturen zum Steigern eines Ansteuerungsstroms und Erhöhen einer Einheitenausbeute bei n-Kohlenstoff-Nanoröhren-Feldeffekttransistoren (CNT-FETs) mit skalierten Kontakten mithilfe einer Benetzungsschicht. Bei einigen Ausführungsformen der Erfindung wird eine Nanoröhre über einer Fläche eines Substrats ausgebildet. Eine Isolationsschicht wird so über der Nanoröhre ausgebildet, dass Endabschnitte der Nanoröhre freiliegen. Ein Metall mit niedriger Austrittsarbeit wird über den Endabschnitten der Nanoröhre ausgebildet, und eine Benetzungsschicht wird zwischen dem Metall mit niedriger Austrittsarbeit und der Nanoröhre ausgebildet.

公开(公告)号：GB2507686B

公开(公告)日：2014-07-16

申请号：GB201402301

申请日：2011-04-26

Applicant: IBM

Inventor： CHEN KUAN-NENG ,  LIN YU-MING ,  AVOURIS PHAEDON ,  FARMER DAMON BROOKS

IPC: H01L29/16 ,  H01L21/822

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

公开(公告)号：GB2507686A

公开(公告)日：2014-05-07

申请号：GB201402301

申请日：2011-04-26

Applicant: IBM

Inventor： CHEN KUAN-NENG ,  LIN YU-MING ,  AVOURIS PHAEDON ,  FARMER DAMON BROOKS

IPC: H01L29/16 ,  H01L21/822

Abstract: Graphene-channel based transistor comprising a substrate with a source and a drain contact 2102, and a graphene channel 2502 formed on the substrate 1704 which connects the contacts. A gate contact 2902 over the graphene channel, separated from the channel with a dielectric. The gate contact is positioned in a non-overlapping position with the source and drain contacts; this leaves exposed sections 3102 of the graphene channel, which can then be doped with an n-type or p-type dopant 3302. A capping layer may be provided over the source, drain and gate contacts, as well as the exposed sections of the graphene channel. The substrate may comprise an insulating layer on the channel. The substrate may comprise an insulating wafer or a wafer having an insulating over layer or a silicon carbide layer. The capping layer may comprise an oxide or a nitride material. There may be more than one layer of graphene on the substrate and this may be deposited using exfoliation or by silicon sublimation with epitaxy.

公开(公告)号：SG184823A1

公开(公告)日：2012-11-29

申请号：SG2012075578

申请日：2011-04-26

Applicant: IBM

Inventor： CHEN KUAN-NENG ,  LIN YU-MING ,  AVOURIS PHAEDON ,  FARMER DAMON BROOKS

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.