公开(公告)号：GB2521517A

公开(公告)日：2015-06-24

申请号：GB201418871

申请日：2014-10-23

Applicant: IBM

Inventor： BAYRAM CAN ,  SADANA DEVENDRA ,  BEDELL STEPHEN ,  OTT JOHN ,  FOGEL KEITH

IPC: H01L31/18

Abstract: A spall releasing plane 15 is formed in the middle of and embedded within a Group III nitride material layer 14. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions and can be formed by adding impurities during the vapour deposition process. Device layer 16, stressor layer 22 and handle 24 are deposited onto the upper surface of the material layer. An edge exclusion layer 18 and adhesion layer 20 can be added above the device layer to aide in the spalling process. This method overcomes the issue of having a lattice mismatch when using Group III nitride materials, e.g. GaN, AlN, InGaN.

公开(公告)号：GB2493244A

公开(公告)日：2013-01-30

申请号：GB201210426

申请日：2012-06-13

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  SADANA DEVENDRA

IPC: H01L31/18

Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer 16 to a base substrate. The stressor layer has a stressor layer portion 16A located atop an upper surface (12, fig. 1) of the base substrate 10 and a self-pinning stressor layer portion 16B located adjacent each sidewall edge of the base substrate. A spalling inhibitor (20) is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion by applying a laser or chemical etch to the self-pinning stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion to control the spalling.

公开(公告)号：GB2492444A

公开(公告)日：2013-01-02

申请号：GB201208147

申请日：2012-05-10

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  CORTES NORMA EDITH SOSA ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

IPC: H01L31/18

Abstract: A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region (14) where the stressor layer (16) is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In a preferred embodiment of the present invention, the method includes forming an edge exclusion material (14) on an upper surface and near an edge of a base substrate (10â â ). A stressor layer (16) is then formed on exposed portions of the upper surface of the base substrate (10â â ) and atop the edge exclusion material (14). A portion (10â ) of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled and separated from the bulk of the substrate. The material is removed from the substrate by stresses caused by the stressor layer. An adhesive layer (15) can be formed between the substrate and stressor layer. This method improves the reusability of the substrate.

公开(公告)号：GB2489830A

公开(公告)日：2012-10-10

申请号：GB201206801

申请日：2011-02-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  KIM JEE HWAN ,  INNS DANIEL ,  SADANA DEVENDRA ,  FOGEL KEITH ,  VICHICONTI JAMES

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/30

Abstract: A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped Si Ge layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron- doped SiGe layer is configured to propagate a fracture at an interface between the boron- doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.

公开(公告)号：AU2020384654A1

公开(公告)日：2022-05-12

申请号：AU2020384654

申请日：2020-11-10

Applicant: IBM

Inventor： ADIGA VIVEKANANDA ,  WYMORE BENJAMIN ,  FOGEL KEITH ,  SANDBERG MARTIN

IPC: H01L39/24 ,  G06N10/00 ,  H01L27/18 ,  H01L39/02 ,  H01L39/22

Abstract: A method of making a Josephson junction for a superconducting qubit includes providing a substructure (500) having a surface with first and second trenches (306 and 308) perpendicular to each other defined therein. The method further includes evaporating a first superconducting material (700) to deposit the first superconducting material and evaporating a second superconducting material (701) to deposit the second superconducting material in the first trench to provide a first lead (710), and forming an oxidized layer (800) on the first and second superconducting materials. The method includes evaporating a third superconducting material (900) at an angle substantially perpendicular to the surface (502) of the substructure to deposit the third superconducting material in the second trench without rotating the substructure to form a second lead (910). A vertical Josephson junction is formed at the intersection of the first and second trenches electrically connected through the first lead and through the second lead.

公开(公告)号：GB2521517B

公开(公告)日：2015-12-30

申请号：GB201418871

申请日：2014-10-23

Applicant: IBM

Inventor： BAYRAM CAN ,  SADANA DEVENDRA ,  BEDELL STEPHEN ,  OTT JOHN ,  FOGEL KEITH

IPC: H01L31/18

Abstract: A spall releasing plane is formed embedded within a Group III nitride material layer. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions that provide the Group III nitride material layer and embed the spall releasing plane. The spall releasing plane provides a weakened material plane region within the Group III nitride material layer which during a subsequently performed spalling process can be used to release one of the portions of Group III nitride material from the original Group III nitride material layer. In particular, during the spalling process crack initiation and propagation occurs within the spall releasing plane embedded within the original Group III nitride material layer.

公开(公告)号：GB2489830B

公开(公告)日：2014-08-20

申请号：GB201206801

申请日：2011-02-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  KIM JEE HWAN ,  INNS DANIEL ,  SADANA DEVENDRA ,  FOGEL KEITH ,  VICHICONTI JAMES

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/30

Abstract: A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped SiGe layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron-doped SiGe layer is configured to propagate a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.

公开(公告)号：GB2493244B

公开(公告)日：2013-06-26

申请号：GB201210426

申请日：2012-06-13

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  SADANA DEVENDRA

IPC: H01L31/18

Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.