公开(公告)号：BR112021021816A8

公开(公告)日：2022-01-18

申请号：BR112021021816

申请日：2020-03-20

Applicant: IBM

Inventor： VIVEKANANDA ADIGA ,  KUMAR ARVIND ,  HERTZBERG JARED ,  RUBIN JOSHUA ,  BRINK MARKUS ,  ROSENBLATT SAMI

IPC: H01L23/532 ,  G06N10/00 ,  H01L27/18 ,  H01L39/02 ,  H01L39/24

Abstract: fabricação de via através de silício em dispositivos quânticos planares. em uma primeira camada supercondutora (316) depositada em uma primeira superfície de um substrato (312), um primeiro componente de um ressonador é padronizado. em uma segunda camada supercondutora (326) depositada em uma segunda superfície do substrato (312), um segundo componente do ressonador é padronizado. a primeira superfície e a segunda superfície são dispostas em relação uma à outra em uma disposição não coplanar. no substrato, um recesso é criado, o recesso se estendendo da primeira camada supercondutora para a segunda camada supercondutora. em uma superfície interna do recesso, uma terceira camada supercondutora (322) é depositada, a terceira camada supercondutora formando um caminho supercondutor entre a primeira camada supercondutora e a segunda camada supercondutora. o excesso de material da terceira camada supercondutora é removido da primeira superfície e da segunda superfície, formando um uma via através de silício (tsv) completa(320).

公开(公告)号：SG11202110210PA

公开(公告)日：2021-10-28

申请号：SG11202110210P

申请日：2020-05-13

Applicant: IBM

Inventor： LEWANDOWSKI ERIC ,  WEBB BUCKNELL ,  HERTZBERG JARED ,  SANDBERG MARTIN ,  JINKA OBLESH

IPC: H01L23/44

Abstract: A thermalization structure is formed using a foil and a low temperature device (LTD). The foil includes a first layer of a first material. The LTD includes a surface from which heat is transferred away from the LTD. A coupling is formed between the foil and the surface of the LTD, where the coupling includes a bond formed between the foil and the surface such that forming the bond forms a set of ridges in the foil, a ridge in the set of ridges operating to dissipate the heat.

公开(公告)号：AU2020265711A1

公开(公告)日：2021-09-30

申请号：AU2020265711

申请日：2020-03-20

Applicant: IBM

Inventor： RUBIN JOSHUA ,  HERTZBERG JARED ,  ROSENBLATT SAMI ,  VIVEKANANDA ADIGA ,  BRINK MARKUS ,  KUMAR ARWIND

IPC: H01L27/18 ,  G06N10/00 ,  H01L23/532 ,  H01L39/02 ,  H01L39/24

Abstract: On a first superconducting layer (316) deposited on a first surface of a substrate (312), a first component of a resonator is pattered. On a second superconducting layer (326) deposited on a second surface of the substrate (312), a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer (322) is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via TSV (320).

公开(公告)号：AU2020262057A1

公开(公告)日：2021-09-30

申请号：AU2020262057

申请日：2020-03-27

Applicant: IBM

Inventor： CROSS ANDREW ,  CHAMBERLAND CHRISTOPHER ,  GAMBETTA JAY MICHAEL ,  HERTZBERG JARED ,  YODER THEODORE ,  ZHU GUANYU

IPC: G06N10/00

Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.

公开(公告)号：CA3137264A1

公开(公告)日：2020-10-29

申请号：CA3137264

申请日：2020-03-27

Applicant: IBM

Inventor： CROSS ANDREW ,  CHAMBERLAND CHRISTOPHER ,  GAMBETTA JAY MICHAEL ,  HERTZBERG JARED ,  YODER THEODORE ,  ZHU GUANYU

Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.