公开(公告)号：JPH1116907A

公开(公告)日：1999-01-22

申请号：JP14774298

申请日：1998-05-28

Applicant: IBM

Inventor： ARUPU BATTAACHATSUYA ,  LEIDY ROBERT K

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/528

Abstract: PROBLEM TO BE SOLVED: To separate an element noise source from signal surfaces by a method wherein the signal surfaces are arranged between two conductive surfaces while logic levels are arranged adjacently to the first conductive surface to be connected to the signal surface through the intermediary of at least one each of the conductive surface. SOLUTION: The conductive metallic levels 34 preferably at the same potential of the logical levels as an insulator 84 insulating the individual potential levels are provided on the third layer. When e.g. copper patterns (wiring and via patterns) are adopted, the noise loss due to the wiring resistance in an element architecture can be reduced, Besides, the insulator 84 is used so as to guarantee that pertinent circuit connection only can be secured. Furthermore, a flat conductive surface 15 set up to the potential equivalent to that of the earth to be beneath another insulator 88 is provided on the metallic levels 34. On the other hand, a partial metallic level 40 above the conductive surface 15 is to be used as a circuit for transmitting signals.

公开(公告)号：JP2005316492A

公开(公告)日：2005-11-10

申请号：JP2005131399

申请日：2005-04-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EMILY F GALLAGHER ,  LEIDY ROBERT K ,  MICHAEL J LASELL ,  KENNETH C RACETTE ,  ANDREW J WATTS

IPC: G03F1/14 ,  G02B5/22 ,  G03F7/00 ,  G03F7/20

CPC classification number: G03F1/64 ,  G03F1/62 ,  G03F7/70983

Abstract: PROBLEM TO BE SOLVED: To provide an improved monolithic hard pellicle to be used for photolithography. SOLUTION: When the starting pellicle plate has original thickness of about 4 mm to about 5 mm, the bulk pellicle plate material may be removed at the center of a membrane such that a remaining pellicle plate material 23 at the bottom of a recessed portion 24 has a thickness ranging from about 200 μm to about 900 μm, more preferably from about 300 μm to about 800 μm, depending on its ultimate use or mounting position. However, the remaining pellicle plate material 23 may have a thickness smaller than 200 μm or greater than 900 μm depending on the predetermined desired thickness of the bottom optical pellicle portion of the resultant pellicle 20 as well as its ultimate use. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于光刻的改进的单片硬质薄膜。 解决方案：当起始防护薄膜组件的原始厚度为约4毫米至约5毫米时，散装防护薄片材料可以在膜的中心处被去除，使得残留的防护薄膜组件板23在凹进的底部 部分24的厚度范围为约200μm至约900μm，更优选为约300μm至约800μm，这取决于其最终用途或安装位置。 然而，剩余的防护薄膜组件23可以具有小于200μm或大于900μm的厚度，这取决于所得防护薄膜组件20的底部光学薄膜部分的预定所需厚度以及其最终用途。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH10335486A

公开(公告)日：1998-12-18

申请号：JP12100598

申请日：1998-04-30

Applicant: IBM

Inventor： JEFFREY S BROWN ,  STEPHEN J HORMES ,  LEIDY ROBERT K ,  VOLDMAN STEVEN H

IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/866

Abstract: PROBLEM TO BE SOLVED: To form a buried Zener diode having a sufficiently low breakdown voltage level, by generating a self-aligning Zener diode by executing a two-state photography mask process in a hybrid photoresist process. SOLUTION: A positive line pattern is formed on an N-well area, and a negative line pattern is formed on the other area than the N-well area. After N-well sedge implant 2302 is formed, the positive line pattern is removed and an N-well 2402 is formed. Then, a positive line pattern 2510 is formed on a p-well area and a negative line pattern 2508 is formed on the other area than the P-well area. Thereafter, an embedded Zener diode is formed by forming P-well edge implant 2602. Therefore, the number of required process masks can be reduced and the alignment problem of the photolightography can be reduced.

公开(公告)号：JPH10335465A

公开(公告)日：1998-12-18

申请号：JP11651698

申请日：1998-04-27

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  GEFFKEN ROBERT M ,  LAM CHUNG H ,  LEIDY ROBERT K

IPC: H01L21/82 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide an antifuse structure and method for personalizing a semiconductor device which can overcome the limitations of the prior art. SOLUTION: An antifuse 100 of the preferred embodiment comprises a two layer transformble insulator core between two electrodes 102, 104. The transformable insulator core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes 102, 104. The two layer core preferably comprises an injector layer 106 and a dielectric layer 108. The injector layer 106 preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer 106 and the dielectric layer 108 are non-conductive. When a sufficient voltage is applied, the core fuses together and becomes conductive.

公开(公告)号：CA2719684A1

公开(公告)日：2009-12-10

申请号：CA2719684

申请日：2009-06-04

Applicant: IBM

Inventor： JAFFE MARK D ,  GAMBINO JEFFREY P ,  LEIDY ROBERT K ,  MUSANTE CHARLES F ,  RASSEL RICHARD J

IPC: H01L27/00

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer (22) with respect to a planarizing layer (18) within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer (20') of different dimensions than active lens layer (20) located over a circuitry portion (Rl) of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture (A) within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion (Rl) within the particular image sensor structures.