公开(公告)号：JP2000223684A

公开(公告)日：2000-08-11

申请号：JP2000017676

申请日：2000-01-26

Applicant: IBM

Inventor： AJMERA ATUL ,  LEOBANDUNG EFFENDI ,  RAUSCH WERNER ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM G

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/52 ,  H01L23/58 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a substrate contact in a substrate with a silicon-on-insulator region. SOLUTION: A shallow isolation trench is formed in a silicon-on-insulator. The shallow isolation trench is filled. A photoresist is glued onto a substrate. A contact trench is formed in the substrate through the filled, shallow isolation trench, the silicon-on-insulator, and a silicon substrate 3 at the lower side of the silicon-on-insulator. The contact trench is filled, a material 21 for filling the contact trench forms a contact to the silicon substrate 3, and grounds the substrate 3, thus solving the problem of the accumulation of static charge in the substrate 3.

公开(公告)号：WO2013181117A3

公开(公告)日：2014-04-03

申请号：PCT/US2013042772

申请日：2013-05-24

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  HEKMATSHOARTABARI BAHMAN ,  LAURO PAUL A ,  LI NING ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

IPC: H01L31/18

CPC classification number: H01L31/0684 ,  H01L21/02002 ,  H01L31/1896 ,  Y02E10/547

Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.

Abstract translation: 以受控剥落方式使用的应力层通过使用可以断裂或溶解的裂开层去除。 在主体半导体衬底和金属应力层之间形成切割层。 受控的剥落过程将相对薄的残余主体衬底层与主体衬底分离。 在将手柄衬底附接到残留衬底层或随后在其上形成的其它层之后，解理层被溶解或以其他方式受到损害以便于去除应力层。 这种去除允许制造双面太阳能电池。

公开(公告)号：WO2005024899A3

公开(公告)日：2008-11-20

申请号：PCT/US2004020850

申请日：2004-06-29

Applicant: IBM ,  PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

Abstract: Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height. The method forms a laminated structure having a substrate, a gate conductor (13) above the substrate, and at least one sacrificial layer (14-16) above the gate conductor (13). The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers (60) adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions (71) adjacent the gate stack, and removes the spacers (60) and the sacrificial layer (14-16).

Abstract translation: 公开了一种形成栅极高度降低的集成电路晶体管的方法和系统。 该方法形成具有衬底，在衬底上方的栅极导体（13）和栅极导体（13）上方的至少一个牺牲层（14-16）的叠层结构。 该过程将层叠结构图案化为从衬底延伸的至少一个栅极堆叠，与栅极叠层相邻形成间隔物（60），不会由间隔物掺杂衬底的区域，以形成邻近栅极的源区和漏区（71） 并且移除间隔物（60）和牺牲层（14-16）。

公开(公告)号：WO2012118719A3

公开(公告)日：2014-04-24

申请号：PCT/US2012026670

申请日：2012-02-25

Applicant: IBM ,  LIU ZIHONG ,  SHAHIDI GHAVAM G

Inventor： LIU ZIHONG ,  SHAHIDI GHAVAM G

IPC: G01N27/327

CPC classification number: H01L29/78684 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/823475 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/12 ,  H01L29/1606 ,  H01L51/0048 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit multilayer integration techniques are provided. In one aspect, a method of fabricating an integrated circuit is provided. The method includes the following steps. A substrate is provided. A plurality of interconnect layers are formed on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack. At least one transistor is formed on a top-most layer of the stack.

Abstract translation: 提供集成电路多层集成技术。 一方面，提供一种制造集成电路的方法。 该方法包括以下步骤。 提供基板。 在布置在堆叠中的基板上形成多个互连层，每个互连层包括一个或多个金属线，其中给定的一个互连层中的金属线大于互连层中的金属线（如果存在） 在堆叠中的给定互连层之上，并且其中给定互连层中的金属线小于互连层中的金属线（如果存在），则低于堆叠中的给定互连层。 在堆叠的最顶层上形成至少一个晶体管。

公开(公告)号：WO2007005145A3

公开(公告)日：2007-03-22

申请号：PCT/US2006020221

申请日：2006-05-25

Applicant: IBM ,  BOYD DIANE C ,  IEONG MEIKEI ,  KEDZIERSKI JAKUB TADEUSZ ,  SHAHIDI GHAVAM G

Inventor： BOYD DIANE C ,  IEONG MEIKEI ,  KEDZIERSKI JAKUB TADEUSZ ,  SHAHIDI GHAVAM G

IPC: H01L29/47 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/94 ,  H01L31/058

CPC classification number: H01L29/66643 ,  H01L29/66772 ,  H01L29/78654

Abstract: An ultra thin SOl MOSFET device structure and method of fabrication is presented. The device has a terminal (20) composed o suicide, which terminal is forming a Schottky contact with the channel (30). A plurality of impurities (70) are segregated on the silicide/channel interface (60), and these segregated impurities determine the resistance of the Schottky contact. Such impurity segregation is achieved by a so called silicidation induced impurity segregation process. Silicon substitutional impurities are appropriate for accomplishing such a segregation.

Abstract translation: 提出了一种超薄的SO1 MOSFET器件结构及其制造方法。 该装置具有由硅化物组成的端子（20），该端子与通道（30）形成肖特基接触。 多个杂质（70）被分离在硅化物/沟道界面（60）上，这些分离的杂质决定了肖特基接触的电阻。 这种杂质偏析通过所谓的硅化物诱导的杂质分离过程来实现。 硅替代杂质适合于实现这种分离。

公开(公告)号：DE112015000221T5

公开(公告)日：2016-08-18

申请号：DE112015000221

申请日：2015-01-20

Applicant: IBM

Inventor： HEKMATSHOARTABARI BAHMAN ,  SHAHIDI GHAVAM G

IPC: H01L29/812 ,  H01L27/095 ,  H01L29/80

Abstract: Übergangs-Feldeffekttransistor (JFET) mit einem Gate-Bereich, der zwei separate Sub-Bereiche, die ein Material mit unterschiedlichen Leitfähigkeitstypen aufweisen, und/oder einen Schottky-Übergang beinhaltet, der einen Gate-Strom im Wesentlichen unterdrückt, wenn der Gate-Übergang in Vorwärtsrichtung vorgespannt ist, ebenso wie Komplementär-Schaltkreise, die derartige JFET-Einheiten umfassen.

公开(公告)号：GB2498854A

公开(公告)日：2013-07-31

申请号：GB201300575

申请日：2013-01-14

Applicant: IBM

Inventor： SHAHRJERDI DAVOOD ,  HEKMATSHOARTABARI BAHMAN ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/80

Abstract: A wide band gap semiconductor buffer layer is incorporated between the channel and an insulating support layer. The conduction band offset of the buffer layer with the channel layer is sufficiently large to confine electron carriers within the channel. The buffer layer also reduces the presence of interface traps, which cause degradation of charge carriers in the channel, caused by the presence of the insulating material. The conduction band offset between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of InGaAs or InGaSb with varying compositions of indium and gallium. The wide bandgap material can be comprised of InAlAs AlGaAs or InGaP with varying compositions of indium, aluminium or gallium. The wide bandgap material may comprise an embedded silicon delta-doped layer which provides electrons to the channel layer.

公开(公告)号：DE102012218265A1

公开(公告)日：2013-04-18

申请号：DE102012218265

申请日：2012-10-08

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  HEKMATSHOAR-TABARI BAHMAN ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

IPC: H01L31/0725 ,  H01L31/18

Abstract: Es wird eine Mehrfachübergang-III-V-Photovoltaikeinheit bereitgestellt, die wenigstens eine obere Zelle, die aus wenigstens einem III-V-Verbindungs-Halbleitermaterial besteht und eine untere Zelle in Kontakt mit einer Oberfläche der wenigstens einen oberen Zelle aufweist. Die untere Zelle weist eine Germanium-enthaltende Schicht in Kontakt mit der wenigstens einen oberen Zelle, wenigstens eine intrinsische hydrierte Silicium-enthaltende Schicht in Kontakt mit einer Oberfläche der Germanium-enthaltenden Schicht und wenigstens eine dotierte hydrierte Silicium-enthaltende Schicht in Kontakt mit einer Oberfläche der wenigstens einen intrinsischen hydrierten Silicium-enthaltenden Schicht auf. Die intrinsischen und dotierten Silicium-enthaltenden Schichten können amorph, nano/mikrokristallin, polykristallin oder einkristallin sein.

公开(公告)号：DE112012000962T5

公开(公告)日：2013-11-21

申请号：DE112012000962

申请日：2012-01-26

Applicant: IBM

Inventor： KHAKIFIROOZ ALI ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD ,  HEKMATSHOAR-TABARI BAHMAN

IPC: H01L21/00

Abstract: Ein Epitaxieverfahren umfasst das Bereitstellen (402) einer frei liegenden kristallinen Zone eines Substratmaterials. Silicium wird in einem Niedertemperaturverfahren epitaxial auf dem Substratmaterial abgeschieden (404), wobei eine Abscheidungstemperatur weniger als 500°C beträgt. Ein Quellengas wird mit einem Verdünnungsgas mit einem Gasverhältnis des Verdünnungsgases zum Quellengas von weniger als 1.000 verdünnt (408).

公开(公告)号：GB2486839B

公开(公告)日：2013-09-04

申请号：GB201204634

申请日：2010-09-08

Applicant: IBM

Inventor： CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE ,  SHAHIDI GHAVAM G

IPC: H01L29/78 ,  H01L21/336

Abstract: A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.