公开(公告)号：DE69122860D1

公开(公告)日：1996-11-28

申请号：DE69122860

申请日：1991-07-06

Applicant: IBM

Inventor： TAST HANS-WERNER ,  PFLUEGER THOMAS ,  GETZLAFF KLAUS JOERG DIPL ING

IPC: G06F7/00 ,  G06F7/76 ,  H03K17/00 ,  H03M7/00 ,  H04J3/04

Abstract: A multiplexer circuit is described which is built up from a series of smaller submultiplexers (241-247, 251-254). It selects a number of adjacent bits, bytes or words from one register and places them in the same order in a second register. The multiplexer can be used in cache memories or instruction buffers.

公开(公告)号：GB2516477A

公开(公告)日：2015-01-28

申请号：GB201313191

申请日：2013-07-24

Applicant: IBM

Inventor： HABERMANN CHRISTIAN ,  RECKTENWALD MARTIN ,  KOCH GERRIT ,  TAST HANS-WERNER ,  JACOBI CHRISTIAN

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0897 ,  G06F12/1045 ,  G06F12/123

Abstract: A multi-level cache hierarchy structure with a first level, Ll, cache, being connected to a second level, L2, cache split into a L2 data cache directory and a L2 instruction cache. The L2 data cache directory comprises directory entries comprising information of data currently stored in the L1 cache. The first level cache is virtually indexed while the second and third levels are physically indexed, and allocating counter bits in a directory entry of tie L2 data cache directory for storing a counter number. The directory entry corresponds to at least one first Ll cache line; performing a first search in the Ll cache for a requested virtual memory address, wherein the virtual memory address corresponds to a physical memory address tag at a second L1 cache line. The directory entry may include least recently used bits to indicate cache lines for data replacement. The directory may be updated with a synonym index.

公开(公告)号：GB2507759A

公开(公告)日：2014-05-14

申请号：GB201220121

申请日：2012-11-08

Applicant: IBM

Inventor： TAST HANS-WERNER ,  RECKTENWALD MARTIN ,  HABERMANN CHRISTIAN ,  JACOBI CHRISTIAN

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0897

Abstract: A hierarchical cache 1 for a data processing system comprises a third level L3 cache 300, a second level L2 cache 200 and a first level L1 cache100. The first level cache is divided into a level one instruction L1i cache 10 and a level one data L1d cache 20. Similarly, the second level cache is divided into a level two instruction (L2i) cache 30 and a level two data (L2d) cache 40. The level three cache is a unified cache. The L1i cache can request data from the L2i cache, which can request data from the L3 cache. The L1d cache can request data from the L2i cache and the L3 cache. The L1 caches are indexed with virtual addresses, whereas the L2 and L3 caches are indexed with physical addresses. The L2 caches translate real addresses to virtual addresses.

公开(公告)号：DE19848742C2

公开(公告)日：2002-05-02

申请号：DE19848742

申请日：1998-10-22

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  PFEFFER ERWIN ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F9/28

Abstract: A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.

公开(公告)号：DE10110576A1

公开(公告)日：2001-10-11

申请号：DE10110576

申请日：2001-03-06

Applicant: IBM

Inventor： HOFSTEE PETER ,  LEENSTRA JENS ,  TAST HANS-WERNER ,  WENDEL DIETER

IPC: G01R31/3185 ,  G06F11/26

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

公开(公告)号：DE19855806A1

公开(公告)日：1999-07-29

申请号：DE19855806

申请日：1998-12-03

Applicant: IBM

Inventor： HILGENDORF ROLF ,  LAUB OLIVER ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F9/42 ,  G06F12/0875 ,  G06F12/08

Abstract: The program branching evaluation is performed by a unit (20) that addresses a table of protocols (22) . The same information is fed to jump instruction identification unit (24). Coupled to the identification unit and receiving data from the table is a cache memory (26). This connects to a selector (30) that provides the next address to be read. An Independent claim is included for a method for executing subroutines and jump operations.

公开(公告)号：GB2456405B

公开(公告)日：2012-05-02

申请号：GB0822457

申请日：2008-12-10

Applicant: IBM

Inventor： JACOBI CHRISTIAN ,  FABEL SIMON ,  PFLANZ MATTHIAS ,  TAST HANS-WERNER ,  ULRICH HANNO

IPC: G06F12/08 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0893

公开(公告)号：GB2456621A

公开(公告)日：2009-07-22

申请号：GB0822458

申请日：2008-12-10

Applicant: IBM

Inventor： JACOBI CHRISTIAN ,  MITCHELL JAMES RUSSELL ,  PFLANZ MATTHIAS ,  TAST HANS-WERNER ,  ULRICH HANNO

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/0855 ,  G06F13/16

Abstract: Disclosed is a method for controlling the access to a cache memory. The store requests are placed in a store queue 10 and read requests placed in a read queue 12. Priorisation logic 18 decides which queue to forwarded to a cache pipeline 14 using the steps of halting the processing of store requests until, either a group of at least a predetermined minimum number of store requests has been accumulated in the store request queue for being granted access to the cache pipeline 32, or a timeout happens, being defined by a timeout-counter 34, or a fetch request requests data that currently resides in the store queue. When the minimum number of store requests has been accumulated, forwarding the group of store requests for accessing the cache processing pipe for being processed in an overlapping form, and operating the cache pipeline with said group of store requests.

公开(公告)号：DE10110576B4

公开(公告)日：2008-06-12

申请号：DE10110576

申请日：2001-03-06

Applicant: IBM

Inventor： HOFSTEE PETER ,  LEENSTRA JENS ,  TAST HANS-WERNER ,  WENDEL DIETER

IPC: G06F11/26 ,  G01R31/3185

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

公开(公告)号：DE19848742A1

公开(公告)日：1999-06-24

申请号：DE19848742

申请日：1998-10-22

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  PFEFFER ERWIN ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F9/28

Abstract: The system includes an arrangement of physical storage registers which form instances of logical registers. A sequence list associates each logical register with a corresponding physical register, and a connection list associates a physical register which forms an instance of a logical register, to a physical register of an earlier, preceding instance of the same logical register, to form a chain of physical registers according to a sequence of instructions. An Independent claim is provided for a method associating physical registers with logical registers.