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    EMBEDDED DIODE AND ITS FORMATION
    11.
    发明专利
    EMBEDDED DIODE AND ITS FORMATION 失效

    公开(公告)号：JPH10335486A

    公开(公告)日：1998-12-18

    申请号：JP12100598

    申请日：1998-04-30

    Applicant: IBM

    Inventor： JEFFREY S BROWN ,  STEPHEN J HORMES ,  LEIDY ROBERT K ,  VOLDMAN STEVEN H

    IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/866

    Abstract: PROBLEM TO BE SOLVED: To form a buried Zener diode having a sufficiently low breakdown voltage level, by generating a self-aligning Zener diode by executing a two-state photography mask process in a hybrid photoresist process. SOLUTION: A positive line pattern is formed on an N-well area, and a negative line pattern is formed on the other area than the N-well area. After N-well sedge implant 2302 is formed, the positive line pattern is removed and an N-well 2402 is formed. Then, a positive line pattern 2510 is formed on a p-well area and a negative line pattern 2508 is formed on the other area than the P-well area. Thereafter, an embedded Zener diode is formed by forming P-well edge implant 2602. Therefore, the number of required process masks can be reduced and the alignment problem of the photolightography can be reduced.

    LATCH-UP RESISTANT STRUCTURE AND ITS FORMATION
    12.
    发明专利
    LATCH-UP RESISTANT STRUCTURE AND ITS FORMATION 失效

    公开(公告)号：JPH10321807A

    公开(公告)日：1998-12-04

    申请号：JP12094798

    申请日：1998-04-30

    Applicant: IBM

    Inventor： FEI D BAKER ,  JEFFREY S BROWN ,  ROBERT J GAUZAR ,  STEPHEN J HORMES ,  ROBERT K LADY ,  EDWARD J NOWACK ,  VOLDMAN STEVEN H

    IPC: H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

    Abstract: PROBLEM TO BE SOLVED: To improve the latch-up resistance of a CMOS device by forming implants on the edges of an N well and/or a P well by using a hybrid resist and, at the same time, to improve the device density of the CMOS device by promoting the scaling of the device. SOLUTION: A wafer section 2100 can be completed by an appropriate manufacturing method, for example, by forming a device gate, a contact diffusion area, etc. In the wafer section 2100, in addition, N and P contact diffusion areas are formed. In these contact diffusion areas, implants are usually formed on the surface of silicon which is not masked with a polysilicon gate. Therefore, a method and a structure for reducing the latch-up of a CMOS device by forming N and/or P edge implants on the edges of a P-well, N-well, and/or a double well are obtained.

    Method and structure of low-capacitance esd-resistant diode
    13.
    发明专利
    Method and structure of low-capacitance esd-resistant diode 审中-公开
    低电容耐ESD二极管的方法与结构

    公开(公告)号：JP2003282892A

    公开(公告)日：2003-10-03

    申请号：JP2003062095

    申请日：2003-03-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： VOLDMAN STEVEN H

    IPC: H01L21/76 ,  H01L21/329 ,  H01L21/62 ,  H01L21/822 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L29/861

    CPC classification number: H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a diode wherein it has a switching speed exceeding 1 GHz, and its electrostatic capacitance is smaller than 0.1 pF, and further, its breakdown voltage of its ESD-resistance is at least 500 V. SOLUTION: The ESD-resistant diode has a first conduction type anode and a second conduction type cathode provided under the anode. At least one of the anode and the cathode has a plurality of diffusion regions contacted with each other. Each of the anode and the cathode is provided between adjacent separating regions to each other, and its scope is defined by the adjacent separating regions. An n + -region 12 can be formed concurrently with the buried sub-collector of a bipolar transistor. Subsequently, an n - -region 14 can be formed as a portion of the epitaxial growth of the bipolar transistor. A p + -region is formed by using the source/drain of a MOSFET. COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供其开关速度超过1GHz，其静电电容小于0.1pF的二极管，并且其ESD电阻的击穿电压至少为500V。 P>解决方案：耐ESD二极管具有设置在阳极下方的第一导电型阳极和第二导电型阴极。 阳极和阴极中的至少一个具有彼此接触的多个扩散区域。 阳极和阴极中的每一个被设置在彼此相邻的分隔区域之间，其范围由相邻的分隔区限定。 可以与双极晶体管的掩埋子集电极同时形成n + SP + + / - 区域12。 随后，可以形成作为双极晶体管的外延生长的一部分的n - 区域14。 通过使用MOSFET的源极/漏极形成p + 区域。 版权所有（C）2004，JPO

    BIPOLAR TRANSISTOR AND ITS MANUFACTURING METHOD
    14.
    发明专利
    BIPOLAR TRANSISTOR AND ITS MANUFACTURING METHOD 审中-公开

    公开(公告)号：JP2002313799A

    公开(公告)日：2002-10-25

    申请号：JP2002060325

    申请日：2002-03-06

    Applicant: IBM

    Inventor： BRENNAN CIARAN J ,  VOLDMAN STEVEN H

    IPC: H01L21/20 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/117

    Abstract: PROBLEM TO BE SOLVED: To provide an ESD SiGe resistant device used in high-frequency circuits. SOLUTION: This bipolar transistor is provided with a silicon substrate 105, a collector 110 formed on the silicon substrate, and an extrinsic base area 180 forming a intrinsic base area 180A and an internal resistor 240, and it is further provided with a base formed on the collector 110, an emitter 200 formed on the intrinsic base area 180A, and a dielectric layer 160 formed between the extrinsic base area 180B and collector 110, and the extrinsic base area 180B, dielectric layer 160 and collector 110 comprise an internal capacitor 235. The base of the transistor is made of silicon germanium.

    FIELD EFFECT TRANSISTOR
    16.
    发明专利
    FIELD EFFECT TRANSISTOR 失效

    公开(公告)号：JP2000269484A

    公开(公告)日：2000-09-29

    申请号：JP15929699

    申请日：1999-06-07

    Applicant: IBM

    Inventor： BROWN JEFFREY S ,  GAUTHIER ROBERT J ,  VOLDMAN STEVEN H

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/423

    Abstract: PROBLEM TO BE SOLVED: To provide a controllable method for solving the problem of corner parasitic current conduction, at shallow trench isolations having narrow devices. SOLUTION: This field effect transistor has a drain region 14, a polysilicon gate 16, an STI region 18, polysilicon gate conductor 20, a dielectric layer 22, a corner edge oxide film 24 and an MOSFET spacer 26. The corner edge oxide film 24, added to the dielectric layer 22, is formed on the device corners, thereby increasing the thickness of the oxide film on the device corners, as well as its threshold voltage Vt. This reduces both the off-current by the device corner and increases the edge dielectric breakdown voltage. Or this enables reduction of the MOSFET gate induced drain leakage.

    DEPLETED POLYSILICON EDGE MOSFET STRUCTURE AND FABRICATION THEREOF
    17.
    发明专利
    DEPLETED POLYSILICON EDGE MOSFET STRUCTURE AND FABRICATION THEREOF 失效

    公开(公告)号：JP2000101084A

    公开(公告)日：2000-04-07

    申请号：JP26349399

    申请日：1999-09-17

    Applicant: IBM

    Inventor： BROWN JEFFREY S ,  GAUTHIER JR ROBERT J ,  VOLDMAN STEVEN H

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure, especially of FET, in which threshold voltage can be increased in the vicinity of corner of isolating region and a fabrication method thereof. SOLUTION: A field effect transistor has source and drain regions 26, 28, a channel region 24 between them, an isolating region 22 in a substrate, and a gate 30 including gate dopant on the channel region. The isolating region provides the corner region of channel along the interface between the channel region and the isolating region. The gate includes a region where the gate dopant is substantially depleted at least in a region where the channel region and the isolating region overlap and the threshold voltage in the channel corner region beneath the depletion region 34 increases as compared with the channel region between corner regions. A field effect transistor having an MOSFET gate 'corner part' of decreased dopant concentration improves the breakdown strength at the edge.

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