公开(公告)号：CA2659479C

公开(公告)日：2010-07-13

申请号：CA2659479

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L21/18 ,  H01L29/16 ,  H01L29/772 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from the carbon-nanotube by a dielectric film [111].

公开(公告)号：DE60141843D1

公开(公告)日：2010-05-27

申请号：DE60141843

申请日：2001-09-27

Applicant: IBM

Inventor： CANAPERI DONALD ,  CHU JACK OON ,  D EMIC CHRISTOPHER ,  HUANG LIJUAN ,  OTT JOHN ALBERT ,  WONG HON-SUM PHILIP

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/76 ,  H01L27/12 ,  H01L29/778 ,  H01L29/786 ,  H01L29/812

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1-yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC.

公开(公告)号：MY126089A

公开(公告)日：2006-09-29

申请号：MYPI20014195

申请日：2001-09-06

Applicant: IBM

Inventor： CANAPERI DONALD F ,  CHU JACK OON ,  EMIC CHRISTOPHER P D ,  HUANG LIJUAN ,  OTT JOHN ALBERT ,  WONG HON-SUM PHILIP

IPC: H01L21/36 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/778 ,  H01L29/786 ,  H01L29/812

Abstract: A METHOD FOR FORMING STRAINED SI OR SIGE ON RELAXED SIGE ON INSULATOR (SGOJ) IS DESCRIBED INCORPORATING GROWING EPITAXIAL SI1GE LAYERS ON A SEMICONDUCTOR SUBSTRATE, IMPLANTING HYDROGEN INTO A SELECTED SI1..GE LAYER TO FORM A HYDROGENERICH DEFECTIVE LAYER, SMOOTHING SURFACES BY CHEMO-MECHANICAL POLISHING, BONDING TWO SUBSTRATES TOGETHER VIA THEXMAL TREATMENTS AND SEPARATING TWO SUBSTRATES AT THE HYDROGEN-RICH DEFECTIVE LAYER. THE SEPARATED SUBSTRATES MAY HAVE ITS UPPER SURFACE SMOOTHED BY CMI’ FOR EPITAXIAL DEPOSITION OF RELAXED SI,GE,,, AND STRAINED SI1GE DEPENDING UPON COMPOSITION, STRAINED SI, STRAINED SIC, STRAINED GE, STRAINED GEC, AND STRAINED SI3GEC.

公开(公告)号：AU2003215750A1

公开(公告)日：2003-10-27

申请号：AU2003215750

申请日：2003-03-14

Applicant: IBM

Inventor： SOLOMON PAUL ,  WONG HON-SUM PHILIP ,  FISCHETTI MASSIMO ,  LAUX STEVEN

IPC: H01L27/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/04 ,  H01L21/335 ,  H01L29/739 ,  H01L27/088

Abstract: A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.

公开(公告)号：AU2003224668A8

公开(公告)日：2003-10-08

申请号：AU2003224668

申请日：2003-02-19

Applicant: IBM

Inventor： WONG HON-SUM PHILIP ,  COLLINS PHILIP G ,  AVOURIS PHAEDON ,  MARTEL RICHARD ,  APPENZELLER JOERG ,  CHAN KEVIN K

IPC: H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L29/51 ,  H01L51/20

Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

公开(公告)号：CA2695715C

公开(公告)日：2011-06-07

申请号：CA2695715

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L21/335 ,  B82Y40/00 ,  H01L29/772 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from the carbon-nanotube by a dielectric film [111].

公开(公告)号：CA2479024C

公开(公告)日：2010-02-16

申请号：CA2479024

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from 10 the carbon-nanotube by a dielectric film [111].

公开(公告)号：PL373571A1

公开(公告)日：2005-09-05

申请号：PL37357103

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L51/20 ,  H01L29/51

Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

公开(公告)号：AU2003224668A1

公开(公告)日：2003-10-08

申请号：AU2003224668

申请日：2003-02-19

Applicant: IBM

Inventor： MARTEL RICHARD ,  WONG HON-SUM PHILIP ,  APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G

IPC: H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

公开(公告)号：CA2695715A1

公开(公告)日：2003-10-02

申请号：CA2695715

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L21/335 ,  H01L29/772 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from the carbon-nanotube by a dielectric film [111].