公开(公告)号：DE102004019786B3

公开(公告)日：2005-09-01

申请号：DE102004019786

申请日：2004-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of a first contact hole of a memory component comprises forming a semiconductor substrate (10) having a cell field region (20) and a logic region (30), producing an insulating layer (11) on the semiconductor surface, forming a sacrificial layer (12) on the insulating layer, depositing a fist mask layer, structuring the first mask layer to form first mask layer covers, anisotropically etching the sacrificial layer to expose the insulating layer, removing the first mask layer covers, depositing a second mask layer (16), structuring the second mask layer to form second mask layer covers, anisotropically etching the sacrificial layer to expose the insulating layer, removing the second mask layer covers, producing a filler layer between the blocks formed by the sacrificial layer, etching the sacrificial layer to remove the blocks in the filler layer, removing the exposed insulating layer, and filling contact opening regions with a conducting material.

公开(公告)号：DE10314274B3

公开(公告)日：2004-09-16

申请号：DE10314274

申请日：2003-03-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS ,  GENZ OLIVER ,  STAVREV MOMTCHIL ,  VOGT MIRKO

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/283

Abstract: Production of a first contact perforated surface in a storage device having storage cells comprises preparing a semiconductor substrate (1) with an arrangement of gate electrode strips (2) on the semiconductor surface, forming an insulating layer (3) on the semiconductor surface, forming a sacrificial layer on the insulating layer, forming material plugs on the sacrificial layer, producing a glass-like layer (8) exposing sacrificial layer blocks over contact openings between the gate electrode strips, etching the sacrificial material, removing the exposed insulating layer over the contact openings, and filling the contact opening regions with a conducting material (9). The sacrificial layer is formed by depositing a first sacrificial layer on the insulating layer, planarizing and depositing a second sacrificial layer.

公开(公告)号：DE10217386A1

公开(公告)日：2003-11-13

申请号：DE10217386

申请日：2002-04-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  GRAF WERNER

IPC: H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/283

Abstract: Production of electrically conducting contact on substrate comprises forming bars on substrate to form trench between bars, depositing dielectric layer (40) to fill trench to form hollow chamber (50), selectively etching dielectric to form contact hole (60) having base surface (70) in filled trench, depositing insulating layer (80) in contact hole and hollow chamber, etching insulating layer, and filling hole with conducting material. Production of an electrically conducting contact on a substrate comprises preparing a substrate, forming bars with side surfaces facing each other in a partial region on the substrate to form a trench between the bars, depositing a dielectric layer (40) to fill the trench forming a hollow chamber (50) with a cross-section within the dielectric layer in the trench, selectively etching the dielectric layer forming a contact hole (60) having a base surface (70) in a partial section of the filled trench between the bars so that the hollow chamber is opened and the substrate is exposed on the base surface of the contact hole, depositing an insulating layer (80) in the contact hole and in the hollow chamber, etching the insulating layer to expose the substrate on the base surface of the contact hole, and filling the contact hole with a conducting material to form the electrically conducting contact.

公开(公告)号：DE10142595A1

公开(公告)日：2003-03-27

申请号：DE10142595

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  KIESLICH ALBRECHT ,  SACHSE HERMANN ,  FELDNER KLAUS

IPC: H01L21/3105 ,  H01L21/762 ,  H01L21/8242

Abstract: A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.

公开(公告)号：DE102004060346B4

公开(公告)日：2006-10-19

申请号：DE102004060346

申请日：2004-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS ,  HORST JANA

IPC: H01L21/8239

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

公开(公告)号：DE102004060346A1

公开(公告)日：2006-07-20

申请号：DE102004060346

申请日：2004-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS ,  HORST JANA

IPC: H01L21/8239

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

公开(公告)号：DE10342775B4

公开(公告)日：2006-03-23

申请号：DE10342775

申请日：2003-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DRUMMER HEIKE ,  STAECKER JENS ,  FROEHLICH HANS-GEORG ,  GRUSS STEFAN ,  WIENHOLD RALPH ,  GRAF WERNER

IPC: H01L23/544 ,  G03F9/00 ,  H01L21/66 ,  H01L21/8242

公开(公告)号：DE102004020938B3

公开(公告)日：2005-09-08

申请号：DE102004020938

申请日：2004-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  PATZER JOACHIM ,  GRAF WERNER

IPC: H01L21/283 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

Abstract: Producing a primary contact hole plane in a storage building block, comprises preparing a semiconductor substrate with a cell region (20) and a logic region (30), which have adjacent gate electrode sections (21,31) on the semiconductor surface (10). Gate electrode sections have a silicon dioxide cover layer, and an insulating layer (11) is located between them. A silicon dioxide layer (12) in formed on the insulation. A primary mask is applied which is then structured and etched near the gate contact. The mask is then removed and a sacrificial layer is formed followed by a secondary mask. The latter is structured to establish contact openings, which are then etched. The secondary mask is removed and a filling layer is applied between sacrificial layer blocks. The blocks are then removed and the gate electrode and semiconductor surfaces are anisotropically etched.

公开(公告)号：DE10342775A1

公开(公告)日：2005-04-28

申请号：DE10342775

申请日：2003-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DRUMMER HEIKE ,  STAECKER JENS ,  FROEHLICH HANS-GEORG ,  GRUSS STEFAN ,  WIENHOLD RALPH ,  GRAF WERNER

IPC: G03F9/00 ,  H01L21/66 ,  H01L21/8242 ,  H01L23/544

Abstract: When forming the main structure, at least two further structural components (12b) are formed, spaced apart on the wafer (10) substrate (5) surface. They are alignment marks. A trench (26) is formed to join them. Their (12b) spacing, and the trench depth, exceed the layer (14) thickness. In this way, a depression (27) with sidewalls (28) remains in the planarized surface (32) of the layer (14). During alignment of the wafer, the sidewalls (28) are detected. An independent claim is included for the corresponding mark.

公开(公告)号：DE10259634A1

公开(公告)日：2004-07-15

申请号：DE10259634

申请日：2002-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HAFFNER HENNING ,  KOWALEWSKI JOHANNES ,  HEINECK LARS

IPC: H01L21/768 ,  H01L21/8242

Abstract: The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.