公开(公告)号：DE10146509C2

公开(公告)日：2003-07-31

申请号：DE10146509

申请日：2001-09-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  BRAUN GEORG

IPC: H03K5/08 ,  H03K5/24

公开(公告)号：DE10037976C2

公开(公告)日：2003-01-30

申请号：DE10037976

申请日：2000-08-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/06 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: The voltage drop across a word line (VWL) is (V1-V2). A voltage controller applies a voltage (VBL) of (V1 + V2/2) to the bit lines (BLO-BL4). The voltage gradient across the word line (WL) relative to the bit line produces a cell voltage (VZ = VWL-VBL) which reverse along the memory cells. In consequence parasitic currents flow not through the word line but between cells (Z0-Z4) at corresponding positions relative to the center of the word line

公开(公告)号：DE10032271A1

公开(公告)日：2002-01-24

申请号：DE10032271

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.

公开(公告)号：DE10041375B4

公开(公告)日：2005-06-02

申请号：DE10041375

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  MUELLER GERHARD ,  GOGL DIETMAR ,  KANDOLF HELMUT

IPC: G11C11/15 ,  G11C17/16 ,  G11C29/00

公开(公告)号：DE10345550B3

公开(公告)日：2005-02-10

申请号：DE10345550

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  KALMS SVEN ,  KUZMENKA MAKSIM ,  HAUSMANN MICHAEL

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/4096

Abstract: The memory device has an even number of at least 4 random-access memory modules (D), each having a given number of memory cells organized in disjunctive cell groups, the cells in each group simultaneously selected by a cell group address for write-in or read-out of data via a m-bit data bus (DB), connected to an n-bit parallel port (DP) via a data register (DR). The memory modules are divided into at least 2 disjunctive module groups with the least possible difference in their spacings from the data register, a selection device (SR,DS,AB,A) used for selection of a module from the same module group for each m-bit group of the same n-bit packet.

公开(公告)号：DE10146509A1

公开(公告)日：2003-04-24

申请号：DE10146509

申请日：2001-09-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  BRAUN GEORG

IPC: H03K5/08 ,  H03K5/24

Abstract: An input circuit (1) has an adjustable reference-voltage source (9), and includes a comparator circuit (2), which receives the reference voltage and the signal from a bus line (3). The reference voltage source comprises one transistor (7) connected between the supply potential (VDD) and ground (GND), and a terminal connected to the reference voltage input of the comparator (21). The voltage source also has a second transistor (8), and the sources (S3,S4) of the transistors are used to switch the conduction of the transistors. The reference voltage is adjusted by the connected conduction impedances of the conducting transistors.

公开(公告)号：DE10051173C2

公开(公告)日：2002-09-12

申请号：DE10051173

申请日：2000-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C11/15

公开(公告)号：DE10102351A1

公开(公告)日：2002-08-08

申请号：DE10102351

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  LAMMERS STEFAN ,  HOENIGSCHMID HEINZ

IPC: G11C8/00 ,  G11C8/08

公开(公告)号：DE10032271C2

公开(公告)日：2002-08-01

申请号：DE10032271

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.

公开(公告)号：DE10017368A1

公开(公告)日：2001-10-11

申请号：DE10017368

申请日：2000-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  ESTERL ROBERT ,  HOENIGSCHMID HEINZ ,  KANDOLF HELMUT

IPC: G11C11/22

Abstract: The integrated memory device operating method uses a pulsed plate concept for accessing a selected memory cell (MC0) of the memory cell matrix during each access cycle, with initial potentials applied to the column line (BLt) and the plate line (PL) of a required memory cell prior to it being accessed by activation of the row line (WL0), for switching the memory cell selection transistor (T0). The potential applied to the plate line is pulsed so that the during the access cycle the memory capacitor of the selected memory cell is charged and discharged.