公开(公告)号：DE102004061518A1

公开(公告)日：2006-06-29

申请号：DE102004061518

申请日：2004-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ILICALI GUERKAN ,  LANDGRAF ERHARD ,  ROESNER WOLFGANG ,  SPECHT MICHAEL

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12

Abstract: The method involves producing an electrically conductive layer according to production of an insulating area at the insulating area and over a top surface. An auxiliary layer (40) is produced according to the production of the electrically conductive layer. The auxiliary layer covers a part of the electrically conductive layer and does not cover a part of the electrically conductive layer that is arranged over the top surface. An independent claim is also included for an integrated switching arrangement.

公开(公告)号：DE19957303B4

公开(公告)日：2006-05-11

申请号：DE19957303

申请日：1999-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LANDGRAF ERHARD ,  HOFMANN FRANZ

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336

公开(公告)号：AU2003267005A1

公开(公告)日：2004-03-29

申请号：AU2003267005

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  SPECHT MICHAEL ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

公开(公告)号：AU2003264084A8

公开(公告)日：2004-03-29

申请号：AU2003264084

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LANDGRAF ERHARD ,  SCHULZ THOMAS ,  SPECHT MICHAEL ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L29/73 ,  H01L29/76 ,  H01L29/792

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F 2 per bit can thus be achieved.

公开(公告)号：AU2003264084A1

公开(公告)日：2004-03-29

申请号：AU2003264084

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  SPECHT MICHAEL ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L29/73 ,  H01L29/76 ,  H01L29/792

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F 2 per bit can thus be achieved.

公开(公告)号：DE10227605A1

公开(公告)日：2004-01-15

申请号：DE10227605

申请日：2002-06-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN R JOHANNES ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  KRETZ JOHANNES

IPC: H01L21/8242 ,  H01L25/065 ,  H01L21/58 ,  H01L21/283 ,  H01L27/108 ,  H01L27/112

Abstract: A layer system comprises a substrate having a surface processed with a conductive metal structure and an opposite processed second surface. A second substrate is attached by a third surface to the first surface of the first substrate. An independent claim is also included for a process for producing the system above.

公开(公告)号：DE10204873C1

公开(公告)日：2003-10-09

申请号：DE10204873

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LUYKEN HANNES ,  LANDGRAF ERHARD

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

Abstract: Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.

公开(公告)号：DE102018106560A1

公开(公告)日：2019-04-18

申请号：DE102018106560

申请日：2018-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOICESCU EMANUEL ,  BÖHM MATTHIAS ,  WEIDENAUER JANIS ,  JAHN STEFAN ,  LANDGRAF ERHARD ,  WEBER MICHAEL

IPC: H01L23/60 ,  B81B7/02 ,  B81C1/00 ,  G01L9/02 ,  H01L23/49

Abstract: Ein Drucksensorbauelement (2000) umfasst einen Halbleiter-Die (120) des Drucksensorbauelements (2000) und einen Bonddraht (110) des Drucksensorbauelements (2000). Eine maximale vertikale Distanz (2012) zwischen einem Teil des Bonddrahts (110) und dem Halbleiter-Die (120) ist größer als eine minimale vertikale Distanz (2014) zwischen dem Halbleiter-Die (120) und einer Oberfläche eines Gels, das den Halbleiter-Die (2010) bedeckt.

公开(公告)号：DE102011087845B4

公开(公告)日：2015-07-02

申请号：DE102011087845

申请日：2011-12-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTRAMS THOMAS ,  PRIBIL ANDREAS ,  LANDGRAF ERHARD ,  FEICK HENNING ,  DAHL CLAUS

IPC: H01L29/78 ,  H01L21/266 ,  H01L21/283 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/739

Abstract: Transistorbauelement, das aufweist: einen Halbleiterkörper (100); ein in dem Halbleiterkörper (100) angeordnetes aktives Transistorgebiet (110); ein das aktive Transistorgebiet in dem Halbleiterkörper (100) ringförmig umgebendes Isolationsgebiet (120); eine Sourcezone (11), eine Drainzone (12), eine Bodyzone (13) und eine Driftzone (14) in dem aktiven Transistorgebiet (110), wobei die Sourcezone (11) und die Drainzone (12) in lateraler Richtung des Halbleiterkörpers (100) beabstandet sind und die Bodyzone (13) zwischen der Sourcezone (11) und der Driftzone (14) und die Driftzone (14) zwischen der Bodyzone (13) und der Drainzone angeordnet ist; eine Gate- und Feldelektrode (20), wobei die Gate- und Feldelektrode (20) oberhalb des aktiven Transistorgebiets (110) angeordnet ist, das Isolationsgebiet (120) wenigstens im Bereich der Drainzone (12) überlappt, gegenüber dem aktiven Transistorgebiet (100) durch eine Dielektrikumsschicht (30) isoliert ist, die im Bereich der Bodyzone (13) eine erste Dicke (d1) und im Bereich der Driftzone (14) abschnittsweise eine zweite Dicke (d2), die größer als die erste Dicke (d1) ist, aufweist und wobei die Gate- und Feldelektrode (20) eine erste Kontaktöffnung (21) oberhalb der Drainzone (12) aufweist; und eine Drainelektrode (41), die die Drainzone (12) durch die erste Kontaktöffnung (21) kontaktiert.

公开(公告)号：DE10324550B4

公开(公告)日：2006-10-19

申请号：DE10324550

申请日：2003-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  SPECHT MICHAEL ,  LANDGRAF ERHARD

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792

Abstract: An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device can include providing a plurality of u-shaped MOSFETs, which are spaced apart from one another and have a multilayer dielectric. The dielectric suitable for charge trapping along rows in a first direction and alone columns in a second direction in trenches of a semiconductor substrate. Source/drain regions are provided between the u-shaped MOSFETs in interspaces between the rows which run parallel to the columns. Isolation trenches are provided in the source/drain regions between the u-shaped MOSFETs of adjacent columns as far as a particular depth in the semiconductor substrate. The isolation trenches are filled with an insulation material. Word lines are provided for connecting respective rows of u-shaped MOSFETs.