公开(公告)号：DE50209507D1

公开(公告)日：2007-03-29

申请号：DE50209507

申请日：2002-12-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

IPC: H01L23/544 ,  G01R31/26 ,  G01R31/27 ,  G01R31/316 ,  H01L23/60

公开(公告)号：DE10255359A1

公开(公告)日：2004-06-24

申请号：DE10255359

申请日：2002-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WENDEL MARTIN ,  STREIBL MARTIN ,  ESMARK KAI ,  RIESS PHILIPP ,  SCHAFBAUER THOMAS

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

公开(公告)号：DE10162542A1

公开(公告)日：2003-04-10

申请号：DE10162542

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STADLER WOLFGANG ,  BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  STREIBL MARTIN ,  WENDEL MARTIN ,  RIESS PHILIPP

IPC: H01L23/544 ,  H01L23/60 ,  H01L21/66

Abstract: The method involves common production of an integrated circuit and a test structure using the same process steps, measuring electrical parameters on the test structure, driving characteristic values from the measured parameter values that characterize an electrostatic discharge/latch-up characteristic of the integrated circuit and checking whether they are in a define range selected to achieve desired electrostatic discharge/latch-up behavior.

公开(公告)号：DE102012103024B4

公开(公告)日：2016-09-29

申请号：DE102012103024

申请日：2012-04-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIESS PHILIPP ,  SIPRAK DOMAGOJ

IPC: H01L21/329 ,  H01L29/872 ,  H01L29/93

Abstract: Verfahren zum Herstellen eines Halbleiterbauelements (100), wobei das Verfahren Folgendes aufweist: – Bereitstellen eines Substrats (10) mit einem ersten Gebiet und einem zweiten Gebiet; – Ausbilden einer Gatedielektrikumsschicht mindestens über dem zweiten Gebiet des Substrats (10); – Ausbilden einer ersten Dummy-Gateelektrode über dem ersten Gebiet des Substrats (10), wobei die erste Dummy-Gateelektrode eine erste leitende Schicht und eine zweite leitende Schicht über der ersten leitenden Schicht aufweist; – in dem zweiten Gebiet des Substrats (10) Ausbilden einer zweiten Dummy-Gateelektrode über der Gatedielektrikumsschicht, wobei die zweite Dummy-Gateelektrode eine dritte leitende Schicht und eine vierte leitende Schicht über der dritten leitenden Schicht aufweist; – Ausbilden eines ersten dotierten Gebiets (21) unter der ersten Dummy-Gateelektrode; – Ausbilden eines ersten Grabens durch Entfernen der ersten Dummy-Gateelektrode; – Ausbilden eines zweiten Grabens durch Entfernen der vierten leitenden Schicht und – Ausbilden einer Metallschicht über dem Substrat (10), wobei ein erster Abschnitt der Metallschicht das erste dotierte Gebiet (21) in dem ersten Graben elektrisch kontaktiert und ein zweiter Abschnitt der Metallschicht den zweiten Graben mindestens teilweise füllt.

公开(公告)号：DE102005028919B4

公开(公告)日：2010-07-01

申请号：DE102005028919

申请日：2005-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIESS PHILIPP ,  WENDEL MARTIN ,  FEICK HENNING

IPC: H01L23/60

公开(公告)号：DE102008047865A1

公开(公告)日：2010-04-22

申请号：DE102008047865

申请日：2008-09-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUMGARTNER PETER ,  BENETIK THOMAS ,  MEYER-BERG GEORG ,  RIESS PHILIPP

IPC: H01L27/06 ,  H01L21/822

Abstract: The circuit arrangement has multiple metallization planes (102), which extend parallel to a main surface of a semiconductor substrate. A capacitor structure is formed between two metallization planes. The capacitor structure has multiple conducting elements (104-10,104-20). A circuit element is arranged in the former metallization plane. Independent claims are included for the following: (1) a system, which has an analog circuit part; and (2) a method for manufacturing a circuit arrangement in a semiconductor substrate.

公开(公告)号：DE102008054320A1

公开(公告)日：2009-06-04

申请号：DE102008054320

申请日：2008-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  BAUMGARTNER PETER ,  BENETIK THOMAS ,  KALTALIOGLU ERDEM ,  RIESS PHILIPP ,  RUDERER ERWIN ,  TEWS HELMUT ,  GLASOW ALEXANDER VON

IPC: H01L27/08 ,  H01L21/822

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

公开(公告)号：DE10255359B4

公开(公告)日：2008-09-04

申请号：DE10255359

申请日：2002-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WENDEL MARTIN ,  STREIBL MARTIN ,  ESMARK KAI ,  RIESS PHILIPP ,  SCHAFBAUER THOMAS

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

公开(公告)号：FR2827706B1

公开(公告)日：2004-04-09

申请号：FR0209195

申请日：2002-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/74 ,  H01L23/62

Abstract: The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff 1 ) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff 2 ), which is less than the first differential resistance (Rdiff 1 ).

公开(公告)号：GB2382462B

公开(公告)日：2004-01-28

申请号：GB0216883

申请日：2002-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/74 ,  H01L27/02 ,  H01C7/12 ,  H01L45/00

Abstract: The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff 1 ) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff 2 ), which is less than the first differential resistance (Rdiff 1 ).