公开(公告)号：WO2004040668A3

公开(公告)日：2004-07-08

申请号：PCT/DE0303612

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: G11C13/02 ,  H01L29/78 ,  H01L51/00 ,  H01L51/30 ,  H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: The invention relates to a field effect transistor assembly and an integrated circuit array. The field effect transistor assembly contains a substrate, a first wiring plane with a first source/drain region on the substrate and a second wiring plane with a second source/drain region above the first wiring plane. The field effect transistor assembly also comprises at least one vertical nanoelement as a channel region, which is situated between and coupled to both wiring planes. The nanoelement is at least partially surrounded by electrically conductive material, forming a gate region, whereby electrically insulating material is provided between the nanoelement and the electrically conductive material to act as a gate insulating layer.

Abstract translation: 本发明涉及一种场效应晶体管装置和一种电路阵列。 场效应晶体管装置包括衬底，在衬底上具有第一源极/漏极区域的第一布线平面以及在第一布线平面上具有第二源极/漏极区域的第二布线平面。 此外，场效应晶体管装置包含至少一个垂直纳米元件作为沟道区域，其布置在布线平面之间并耦合到两者。 纳米元件至少部分地由导电材料包围的栅极区域，所述电绝缘材料作为纳米元件和所述导电材料之间的栅绝缘层提供。

公开(公告)号：DE112006004212B4

公开(公告)日：2015-07-23

申请号：DE112006004212

申请日：2006-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LI HONG-JYH ,  SCHULZ THOMAS

IPC: H01L27/088 ,  H01L21/8234

Abstract: Halbleiteranordnung (100 bis 500) mit: einem Werkstück (102 bis 502), wobei das Werkstück (102 bis 502) ein erstes Gebiet (104 bis 504) und ein zweites Gebiet (106 bis 506) in der Nähe des ersten Gebiets (104 bis 504) beinhaltet; einem ersten Transistor, der in dem ersten Gebiet (104 bis 504) des Werkstücks (102 bis 502) angeordnet ist, wobei der erste Transistor zumindest zwei erste Gateelektroden (320, 420) und ein erstes Gatedielektrikum (320, 420, 520), das in der Nähe jeder der zumindest zwei ersten Gateelektroden (326, 426, 526) angeordnet ist, beinhaltet; und einem zweiten Transistor, der in dem zweiten Gebiet (106 bis 506) des Werkstücks (102 bis 502) angeordnet ist, wobei der zweite Transistor zumindest zwei zweite Gateelektroden (332, 432, 532) und ein zweites Gatedielektrikum (322, 422, 522), das in der Nähe jeder der zumindest zwei zweiten Gateelektroden (332, 432, 532) angeordnet ist, beinhaltet, wobei das zweite Gatedielektrikum (322, 422, 522) von dem ersten Gatedielektrikum (320, 420, 520) verschieden ist, wobei der erste Transistor ein erster Mehrfach-Gate-Transistor und der zweite Transistor ein zweiter Mehrfach-Gate-Transistor ist, die aus einer Vielzahl von Rippenstrukturen (105 bis 505) gebildet sind, und wobei das erste Gatedielektrikum (320 bis 520) und das zweite Gatedielektrikum (322 bis 522) aus einer einzigen Schicht von Gatedielektrikummaterial gebildet sind, die über der Vielzahl von Rippenstrukturen (105 bis 505) angeordnet ist und die ein implantiertes Fermi-Pinning-Material enthält, das im ersten Mehrfach-Gate-Transistor implantiert ist, aber nicht im zweiten Mehrfach-Gate-Transistor.

公开(公告)号：DE102008001209B4

公开(公告)日：2011-03-17

申请号：DE102008001209

申请日：2008-04-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78

公开(公告)号：DE102009004550A1

公开(公告)日：2009-09-17

申请号：DE102009004550

申请日：2009-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  POSTNIKOV SERGEI ,  SCHULZ THOMAS ,  ARNIM KLAUS VON

IPC: H01L21/283 ,  H01L21/768

公开(公告)号：DE102007054028A1

公开(公告)日：2008-05-21

申请号：DE102007054028

申请日：2007-11-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSS CHRISTIAN ,  GOSSNER HARALD ,  SCHULZ THOMAS

IPC: H01L29/78 ,  H01L21/336

Abstract: A field effect transistor with a fin structure having a first and a second source/drain region; a body region formed within the fin structure and between the first and the second source/drain region; a metallically conductive region formed within a part of the first source/drain region, the metallically conductive region being adjacent to the body region or to a lightly doped region disposed between the body region and the first source/drain region; and a current ballasting region formed within a part of the second source/drain region.

公开(公告)号：DE102005022763A1

公开(公告)日：2006-11-23

申请号：DE102005022763

申请日：2005-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSS CHRISTIAN ,  SCHULZ THOMAS ,  CHAUDHARY NIRMAL

IPC: H01L23/60 ,  G11C7/10 ,  H01L27/085 ,  H03K17/16 ,  H03K19/003

Abstract: An electronic circuit (100) comprises at least one circuit (101) comprising at least one multi-gate functional FET (102) with at least two gates and at least one ESD protection circuit (103) comprising a multi-gate protective FET (104) that is formed partly as an electrical charge carrying reducing transistor. The trigger voltage of the protective FET is less than that of the functional FET. Independent claims are also included for the following: (A) A circuit arrangement as above;and (B) A production process for the above.

公开(公告)号：DE10211335A1

公开(公告)日：2005-06-09

申请号：DE10211335

申请日：2002-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  PACHA CHRISTIAN ,  LUYKEN JOHANNES R ,  LANDGRAF ERHARD

IPC: H01L21/8244 ,  H01L27/11

公开(公告)号：DE50007390D1

公开(公告)日：2004-09-16

申请号：DE50007390

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR

IPC: H01L29/417 ,  H01L21/20 ,  H01L21/336 ,  H01L29/786

Abstract: A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

公开(公告)号：DE10231202A1

公开(公告)日：2004-02-05

申请号：DE10231202

申请日：2002-07-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LANDGRAF ERHARD ,  HOFMANN FRANZ ,  LUYKEN JOHANNES R ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: Vertical transistor memory cell comprises a substrate containing a trench, a first electrically insulated storage region (201a, 201b; 202a, 202b) on a first sidewall of the trench, a second electrically insulated storage region (201c, 201d; 202c, 202d) on a second sidewall of the trench, a first gate region arranged in the trench on a the first storage region, a second gate region coupled with the first gate region on the second storage region, two first source/drain regions, and two second source/drain regions. One of the first source/drain regions is coupled with a lower end section of one of the storage regions and one of second source/drain regions is coupled with an upper end section of one of the storage regions. An Independent claim is also included for: (a) memory cell arrangement containing several vertical memory cells integrated on and/or in a substrate; (b) production of a vertical memory cell; and (c) process for operating a vertical transistor memory cell.

公开(公告)号：DE10135504A1

公开(公告)日：2003-02-06

申请号：DE10135504

申请日：2001-07-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN JOHANNES R ,  HOFMANN FRANZ ,  ROESNER WOLFGANG ,  LANDGRAF ERHARD ,  SCHULZ THOMAS

IPC: B01L3/00 ,  B81B1/00 ,  B82B3/00 ,  B01J19/00 ,  C12Q1/68 ,  G01N33/48

Abstract: Filter construction has at least one passage opening for fluids, covered by at least two intersecting unidimensional nano-structures (28,40) supported at the carrier. The nano structures are formed by nano wires and/or nano tubes, to form pores of nano dimensions. The nano-structures can be moved in relation to each other by an electrical, magnetic and/or piezoelectric system acting on a moving frame (38).