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    12.
    发明专利
    未知

    公开(公告)号：DE10244569B4

    公开(公告)日：2006-08-10

    申请号：DE10244569

    申请日：2002-09-25

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

    IPC: H01L21/336 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51

    Abstract: Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

    An etching process for increasing the structural size of main structures in a semiconductor substrate useful in semiconductor wafer production for increasing their structural density (thickness, sic) and storage capacity
    13.
    发明专利
    An etching process for increasing the structural size of main structures in a semiconductor substrate useful in semiconductor wafer production for increasing their structural density (thickness, sic) and storage capacity 未知

    公开(公告)号：DE10255866A1

    公开(公告)日：2004-06-17

    申请号：DE10255866

    申请日：2002-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LUETZEN JOERN ,  BIRNER ALBERT ,  KUDELKA STEPHAN ,  TEWS HELMUT ,  WEIS ROLF

    IPC: H01L21/306 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/04

    Abstract: A process for increasing the structural density (thickness, sic) and/or storage capacity of structures introduced into a semiconductor wafer (1) by marking (2) in the rupture direction, where the structures by means of a light exposure device and a mask (3) are formed on the wafer. Before formation of the structures the wafer is turned by 45 deg in its plane and is given a marking in a new direction parallel to a (100) crystal orientation. A process for increasing the structural size (density, sic) of main structures (MS) formed in the bulk of a SS by an etching process, in which main structures on one surface of the SS are exchanged in a surface section of the SS by secondary structures arranged in a surface screen (14) and directed with longitudinal and transverse extension parallel to the x and y axes of the surface screen where before etching the longitudinal and transverse extensions of the main structures are twisted relative to the x and y axes of surface screen so that the section of the SS below the secondary MS main structures is made completely available for formation of further MS by means of a further etching process. Independent claims are included for: (1) a structure in a SS comprising a drain with a limiting upper section at the surface of the SS of plan view surface profile with longitudinal sides parallel to the (100) crystal orientation and with rectangular profile in a lower section below an etch resistant protective layer with longitudinal sides parallel to the (110) crystal orientation; (2) an arrangement of structures in which the thickness of the intermediate walls between adjacent structures in the SS is of the order of 100 nm; (3) a process for reduction of leakage current in a selection transistor and a DRAM-cell with storage capacity, where DRAM = dynamic random access memory, with processing of a semiconductor wafer having a DRAM-cell; (4) a DRAM-cell obtained as above and having storage capacity.

    Feuchtigkeitsbarrierenkondensatoren in Halbleiterkomponenten
    15.
    发明专利
    Feuchtigkeitsbarrierenkondensatoren in Halbleiterkomponenten 未知

    公开(公告)号：DE102008059871B4

    公开(公告)日：2018-03-22

    申请号：DE102008059871

    申请日：2008-12-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BARTH HANS-JOACHIM DR ,  TEWS HELMUT

    IPC: H01L27/07 ,  H01L21/822 ,  H01L23/522

    Abstract: Chip (10), aufweisend: einen inneren Bereich, wobei der innere Bereich aktive Schaltkreise (100) aufweist; einen Peripheriebereich, der keine aktiven Schaltkreise (100) enthält; eine in dem Peripheriebereich neben dem inneren Bereich angeordnete innere Kondensatorplatte (300), wobei die innere Kondensatorplatte (300) elektrisch mit einem Spannungsknoten in den aktiven Schaltkreisen verbunden ist; und eine zwischen der inneren Kondensatorplatte (300) und einem Chiprand angeordnete äußere Kondensatorplatte (200), wobei die äußere Kondensatorplatte (200) elektrisch mit einem anderen Spannungsknoten in den aktiven Schaltkreisen (100) verbunden ist, wobei die innere Kondensatorplatte (300) und die äußere Kondensatorplatte (200) beide vertikal gestapelte Metallleitungen (120, 140, 160, 180, 195) und Durchkontaktierungen (110, 130, 150, 170, 190) aufweisen, die äußere Kondensatorplatte (200) eine Feuchtigkeitsbarriere (400) aufweist, die Feuchtigkeitsbarriere (400) zusätzliche Durchkontaktierungen und zusätzliche Längen und Breiten von Metallleitungen aufweist, mindestens ein Teil der vertikal gestapelten Metallleitungen und der Durchkontaktierungen in einem isolierenden low-k-Material angeordnet ist, die äußere Kondensatorplatte (200) durch Rippen (210) mit dem anderen Spannungsknoten in den aktiven Schaltkreisen (100) elektrisch verbunden wird, mindestens ein Teil der Rippen (210) über der inneren Kondensatorplatte (300) angeordnet und in einen Oxidbereich oder Nitridbereich eingebettet ist und wobei sich die äußere Kondensatorplatte (200) vertikal ohne Unterbrechung in den low-k-Materialbereich erstreckt.

    19.
    发明专利
    未知

    公开(公告)号：DE502004009052D1

    公开(公告)日：2009-04-09

    申请号：DE502004009052

    申请日：2004-09-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEWS HELMUT

    IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/161 ,  H01L29/49 ,  H01L29/51

    Abstract: A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material.

    20.
    发明专利
    未知

    公开(公告)号：DE10341576B4

    公开(公告)日：2007-04-19

    申请号：DE10341576

    申请日：2003-09-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： AKATSU HIROYUKI ,  GLUSCHENKOV OLEG ,  PARKINSON PORSHIA SHANE ,  RAMACHANDRAN RAVIKUMAR ,  SETTLEMYER KENNETH T ,  TEWS HELMUT

    IPC: H01L21/8242 ,  H01L21/20

    Abstract: Microelectronic structure is manufactured by: (i) forming set of openings in surface of substrate (10); (ii) forming film stack having layers on each sidewall of openings; (iii) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (iv) thermally nitriding silicon layer on upper portion of structure. Fabrication of microelectronic structure comprises: (a) forming set of openings in surface of substrate; (b) forming film stack having layers on each sidewall of openings; (c) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (d) thermally nitriding silicon layer on upper portion of structure to form nitrided silicon layer having first thickness limited through reaction kinetics and less than barrier thickness. The openings have sidewalls that extend to a common bottom wall. The layers include nitride diffusion barrier layer having a barrier thickness and silicon layer deposited after the barrier layer.

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