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    12.
    发明专利
    未知

    公开(公告)号：DE10344862A1

    公开(公告)日：2004-04-15

    申请号：DE10344862

    申请日：2003-09-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

    13.
    发明专利
    未知

    公开(公告)号：DE10246306A1

    公开(公告)日：2003-04-30

    申请号：DE10246306

    申请日：2002-10-04

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01G4/06

    Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

    14.
    发明专利
    未知

    公开(公告)号：DE10344862B4

    公开(公告)日：2007-12-20

    申请号：DE10344862

    申请日：2003-09-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

    15.
    发明专利
    未知

    公开(公告)号：DE10246306B4

    公开(公告)日：2009-05-07

    申请号：DE10246306

    申请日：2002-10-04

    Applicant: IBM ,  QIMONDA AG

    Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/8242 ,  H01G4/06 ,  H01L21/316 ,  H01L21/321

    Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

    16.
    发明专利
    未知

    公开(公告)号：DE60133214T2

    公开(公告)日：2009-04-23

    申请号：DE60133214

    申请日：2001-11-13

    Applicant: IBM ,  QIMONDA AG

    Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HOH PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

    IPC: H01L21/8242 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8239

    Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

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