公开(公告)号：DE10258201B4

公开(公告)日：2008-07-03

申请号：DE10258201

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： RAJARAO JAMMY ,  KUDELKA STEPHAN ,  MACSTAY IRENE ,  RAHN STEPHEN ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/8242

公开(公告)号：DE10350354B4

公开(公告)日：2007-08-16

申请号：DE10350354

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/318 ,  H01L21/321 ,  H01L21/336 ,  H01L29/04 ,  H01L29/78

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

公开(公告)号：DE10320029A1

公开(公告)日：2003-12-04

申请号：DE10320029

申请日：2003-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOLDBACH MATTHIAS ,  HAUF MANFRED ,  JAMMY RAIARAO ,  MCSTAY IRENE ,  ROUSSEAU JEAN-MARC ,  SCHROEDER UWE ,  SCHUMANN DIRK ,  SEIDL HARALD ,  SELL BERNHARD ,  SHEPARD JOSEPH F ,  TEWS HELMUT

IPC: H01L21/02 ,  H01L21/441 ,  H01L21/4763 ,  H01L21/8242 ,  H01L23/48 ,  H01L27/108

Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

公开(公告)号：DE10344862A1

公开(公告)日：2004-04-15

申请号：DE10344862

申请日：2003-09-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

公开(公告)号：DE10246306A1

公开(公告)日：2003-04-30

申请号：DE10246306

申请日：2002-10-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01G4/06

Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

公开(公告)号：DE10244569A1

公开(公告)日：2003-04-24

申请号：DE10244569

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

Abstract: A semiconductor gate is capped with a pad oxide layer (20), which is bounded by one or more isolation trenches filled with silicon oxide. The pad oxide layer is thickened to a specified thickness to form a sacrificial oxide layer, then the sacrificial oxide layer is stripped and the semiconductor gate is capped with gate oxide layer. An Independent claim is also included for semiconductor structure.

公开(公告)号：DE10344862B4

公开(公告)日：2007-12-20

申请号：DE10344862

申请日：2003-09-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

公开(公告)号：DE102006002940A1

公开(公告)日：2006-10-19

申请号：DE102006002940

申请日：2006-01-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KUDELKA STEPHAN ,  SETTLEMEYER KENNETH ,  TEWS HELMUT

IPC: H01L21/8242

公开(公告)号：DE10350354A1

公开(公告)日：2004-05-27

申请号：DE10350354

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/321 ,  H01L29/78 ,  H01L21/336

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.