公开(公告)号：DE102014003855A1

公开(公告)日：2014-09-18

申请号：DE102014003855

申请日：2014-03-17

Applicant: INTEL CORP

Inventor： MUTHIAH BHARATH ,  RASH WILLIAM BILL ,  HINTON GLENN J ,  DIXON MARTIN G ,  HAHN SCOTT D ,  PAPWORTH DAVID B

IPC: H04N21/2343

Abstract: In einer Ausführungsform wird eine auf Quality-of-Service(QoS)-Kriterien basierende serverseitige Binärübersetzung und Ausführung von Anwendungen auf mehreren Servern unter Verwendung einer verteilten Übersetzung und Ausführung entweder in einer virtualisierten oder nativen Ausführungsumgebung durchgeführt. Die übersetzten Anwendungen werden ausgeführt, um Ausgabeanzeigedaten zu erzeugen, die Ausgabeanzeigedaten werden in ein Medienformat codiert, und der Videostrom wird über ein Netzwerk einer Client-Vorrichtung zugeführt. In einer Ausführungsform unterstützen ein oder mehrere Grafikprozessoren die Hauptprozessoren der Server durch Beschleunigung des Renderns der Anwendungsausgabe, und ein Medienencoder codiert die Anwendungsausgabe in ein Medienformat.

公开(公告)号：HK1012743A1

公开(公告)日：1999-08-06

申请号：HK98113950

申请日：1998-12-17

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  SA REYNOLD V D

IPC: G06F9/38 ,  G06F

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：GB2285526B

公开(公告)日：1998-11-18

申请号：GB9425726

申请日：1994-12-20

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38 ,  G06F9/32

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：GB2287111B

公开(公告)日：1998-08-05

申请号：GB9500762

申请日：1995-01-16

Applicant: INTEL CORP

Inventor： HINTON GLENN J ,  PAPWORTH DAVID B ,  GLEW ANDREW F ,  FETTERMAN MICHAEL ALAN ,  COLWELL ROBERT P

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G09F13/04

Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.

公开(公告)号：SG50456A1

公开(公告)日：1998-07-20

申请号：SG1996001862

申请日：1994-12-20

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38 ,  G06F9/32

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：SG47981A1

公开(公告)日：1998-04-17

申请号：SG1996005873

申请日：1995-01-16

Applicant: INTEL CORP

Inventor： HINTON GLENN J ,  PAPWORTH DAVID B ,  GLEW ANDREW F ,  FETTERMAN MICHAEL A ,  COLWELL ROBERT P

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G09F13/04 ,  G06F15/76 ,  G06F15/82

Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages. The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages. The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.

公开(公告)号：DE4447238A1

公开(公告)日：1995-07-13

申请号：DE4447238

申请日：1994-12-30

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/28

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：DE112016007516T5

公开(公告)日：2019-10-02

申请号：DE112016007516

申请日：2016-12-12

Applicant: INTEL CORP

Inventor： BRANDT JASON W ,  CHAPPELL ROBERT S ,  CORBAL JESUS ,  GROCHOWSKI EDWARD T ,  GUNTHER STEPHEN H ,  GUY BUFORD M ,  HUFF THOMAS R ,  HUGHES CHRISTOPHER J ,  OULD-AHMED-VALL ELMOUSTAPHA ,  SINGHAL RONAK ,  SOTOUDEH SEYED YAHYA ,  TOLL BRET L ,  RAPPOPORT LIHU ,  PAPWORTH DAVID B ,  ALLEN JAMES D

IPC: G06F12/0817

Abstract: Ausführungsformen einer Erfindung einer Prozessorarchitektur werden offenbart. In einer Ausführungsform enthält ein Prozessor einen Decoder, eine Ausführungseinheit, einen kohärenten Cache und eine Zwischenverbindung. Der Decoder dient dazu, einen Befehl zu decodieren, um eine Cachezeile nullzustellen. Die Ausführungseinheit dient dazu, ein Schreibkommando auszustellen, um einen cachezeilengroßen Schreibvorgang von Nullen zu initiieren. Der kohärente Cache dient dazu, das Schreibkommando zu empfangen, um zu ermitteln, ob es einen Hit im kohärenten Cache gibt und ob ein Cachekohärenzprotokollzustand der getroffenen Cachezeile ein modifizierter Zustand oder ein exklusiver Zustand ist, um eine Cachezeile zu konfigurieren, nur Nullen anzuzeigen und um das Schreibkommando hin zur Zwischenverbindung auszustellen. Die Zwischenverbindung dient dazu, in Antwort auf Empfang des Schreibkommandos einen Snoop an jeden mehrerer anderer kohärenter Caches auszustellen, für die ermittelt werden muss, ob es einen Hit gibt.

公开(公告)号：DE4447238B4

公开(公告)日：2005-08-18

申请号：DE4447238

申请日：1994-12-30

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38 ,  G06F9/28

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：DK0661625T3

公开(公告)日：2000-04-03

申请号：DK94307771

申请日：1994-10-21

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  PAPWORTH DAVID B ,  GUPTA ASHWANI KUMAR ,  FETTERMAN MICHAEL ALAN ,  NATARAJAN SUBRAMANIAN ,  SHENOY SUNIL ,  D SA REYNOLD V

IPC: G06F9/38

Abstract: A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.