公开(公告)号：WO2004038583A2

公开(公告)日：2004-05-06

申请号：PCT/US0328783

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/00 ,  G06F9/45 ,  G06F12/08

CPC classification number: G06F12/0888 ,  G06F8/4442 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F12/0897

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a perdetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

Abstract translation: 公开了用于管理第一高速缓存的旁路的方法和设备。 在一个这样的方法中，识别具有大于或等于预定阈值的预期延迟的加载指令。 然后请求安排所识别的加载指令具有预定的等待时间。 然后计划软件程序。 然后将与预定软件程序中的加载指令相关联的实际等待时间与预定等待时间进行比较。 如果实际等待时间大于或等于预定等待时间，则加载指令被标记为绕过第一高速缓存。

公开(公告)号：WO2017112361A3

公开(公告)日：2017-07-27

申请号：PCT/US2016063890

申请日：2016-11-28

Applicant: INTEL CORP

Inventor： MEKKAT VINEETH ,  MARGULIS OLEG ,  AGRON JASON M ,  SCHUCHMAN ETHAN ,  WINKEL SEBASTIAN ,  WU YOUFENG ,  DANKEL GISLE

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07

CPC classification number: G06F9/30185 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3865

Abstract: Embodiments of apparatus and methods for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.

Abstract translation: 这里描述了用于在无序处理器中检测并从不正确的存储器依赖性推测中恢复的设备和方法的实施例。 例如，方法的一个实施例包括：执行第一加载指令; 检测何时第一加载指令在执行期间经历了不良的存储 - 加载转发事件; 跟踪在执行期间由第一加载指令经历的不良存储 - 加载转发事件的发生; 基于所跟踪的事件来控制所述第一加载指令中的S位的启用; 响应于第一加载指令中的启用的S位产生多个加载操作，其中所述多个加载操作的执行产生与来自所述第一加载指令的执行的结果相等的结果。

公开(公告)号：WO2012125200A3

公开(公告)日：2012-11-15

申请号：PCT/US2011067630

申请日：2011-12-28

Applicant: INTEL CORP ,  WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG

IPC: G06F9/48 ,  G06F9/44 ,  G06F15/80

CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract translation: 在异构多核处理系统上动态切换核可以通过在第一处理核上执行程序代码来执行。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能度量比先前确定的核心性能度量好时，可以用信号通知第二处理核心的掉电，并且程序代码的执行可以在第一处理核心上继续。 当第一性能度量不比先前确定的核心性能度量好时，可以将程序代码的执行从第一处理核心切换到第二处理核心。

公开(公告)号：WO2012030466A2

公开(公告)日：2012-03-08

申请号：PCT/US2011046434

申请日：2011-08-03

Applicant: INTEL CORP ,  HU SHILIANG ,  WU YOUFENG

Inventor： HU SHILIANG ,  WU YOUFENG

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/14

CPC classification number: G06F12/0862 ,  G06F2212/1041 ,  G06F2212/502 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种预取引擎，用于检测存储器中的数据访问步进何时落入一个范围内，以计算预测的下一步，以使用预测的下一步来选择性地预取高速缓存行，并且动态地控制预取。 还描述和要求保护其他实施例。

公开(公告)号：WO2004097633A3

公开(公告)日：2006-01-05

申请号：PCT/US2004008585

申请日：2004-03-19

Applicant: INTEL CORP

Inventor： WU YOUFENG

IPC: G06F9/45

CPC classification number: G06F8/445

Abstract: An arrangement is provided for data value recovery in an optimized program by precisely allocating predicate registers to guard branching instructions in the optimized program at compilation time. At execution time, an execution path leading to a recovery point is determined based on values of predicate registers guarding branching blocks. The values of non-current and non-resident data may be recovered at the recovery point according to the determined execution path. Optimization annotations may also be utilized for data value recovery.

Abstract translation: 通过在编译时精确地分配谓词寄存器来保护优化程序中的分支指令，为优化程序中的数据值恢复提供了一种安排。 在执行时，通过保护分支块的谓词寄存器的值确定通向恢复点的执行路径。 可以根据确定的执行路径在恢复点恢复非当前和非驻留数据的值。 优化注释也可用于数据值恢复。

公开(公告)号：WO03029972A8

公开(公告)日：2004-11-04

申请号：PCT/US0227985

申请日：2002-08-30

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/45 ,  G06F9/38

CPC classification number: G06F8/445 ,  G06F8/443

Abstract: A method and apparatus for providing compiler transformation of code using regions with simplified data and control flow and value specialization are described. In one embodiment, the method includes identifying in the code a plurality of potential candidates for value specialization, selecting a group of candidates from the plurality of potential candidates based on a value profile associated with each potential candidate, and determining specialized data for each selected candidate using a corresponding value profile. The method further includes forming a plurality of optimized regions based on corresponding specialized data. Each optimized region includes one or more selected candidates.

公开(公告)号：AU2011305091B2

公开(公告)日：2014-09-25

申请号：AU2011305091

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/06 ,  G06F9/30

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：DE112011104596T5

公开(公告)日：2014-01-16

申请号：DE112011104596

申请日：2011-12-06

Applicant: INTEL CORP

Inventor： SAGER DAVID J ,  RAIKIN SHLOMO ,  DOMER JASON A ,  SASANKA RUCHIRA ,  GABOR RON ,  NUZMAN JOSEPH ,  PELED LEEOR ,  KIM HO-SEOP ,  WU YOUFENG ,  YAMADA KOICHI ,  NGAI TIN-FOOK ,  CHEN HOWARD H ,  BOBBA JAYARAM ,  COOK JEFFREY J ,  SHAIKH OSMAR M ,  SRINIVAS SURESH

IPC: G06F9/30 ,  G06F9/38

Abstract: Systeme, Vorrichtungen und Verfahren für ein Hardware- und Softwaresystem zum automatischen Zerlegen eines Programms in mehrere parallele Threads werden beschrieben. In einigen Ausführungsformen führen die Systeme und Vorrichtungen ein Verfahren zum Zerlegen eines ursprünglichen Codes und/oder einer generierten Thread-Ausführung aus.

公开(公告)号：GB2499762A

公开(公告)日：2013-08-28

申请号：GB201310833

申请日：2011-12-06

Applicant: INTEL CORP

Inventor： SAGER DAVID J ,  SASANKA RUCHIRA ,  GABOR RON ,  RAIKIN SHLOMO ,  NUZMAN JOSEPH ,  PELED LEEOR ,  DOMER JASON A ,  KIM HO-SEOP ,  WU YOUFENG ,  YAMADA KOICHI ,  NGAI TIN-FOOK ,  CHEN HOWARD H ,  BOBBA JAYARAM ,  COOK JEFFREY J ,  SHAIKH OSMAR M ,  SRINIVAS SURESH

IPC: G06F9/38 ,  G06F9/54 ,  G06F11/36

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

公开(公告)号：AU2011296479A1

公开(公告)日：2013-03-14

申请号：AU2011296479

申请日：2011-08-03

Applicant: INTEL CORP

Inventor： HU SHILIANG ,  WU YOUFENG

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.