VACUUM PLASMA PROCESSOR APPARATUS AND METHOD
    11.
    发明申请
    VACUUM PLASMA PROCESSOR APPARATUS AND METHOD 审中-公开
    真空等离子体处理装置和方法

    公开(公告)号:WO0203763A3

    公开(公告)日:2002-12-27

    申请号:PCT/US0120263

    申请日:2001-06-26

    CPC classification number: H01J37/321

    Abstract: 200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.

    Abstract translation: 在相同或几何形状相同的真空等离子体处理室中处理200mm和300mm晶片。 对于不同尺寸的晶片,具有不同几何形状的基本上平面的激励线圈通过经由腔室顶部的电介质窗口向等离子体供应电磁场而将腔室中的可电离气体激发成等离子体。 两个线圈都包括与线圈的中心点同轴的多个对称的基本圆形的匝和至少一个相对于线圈中心点不对称的匝。 两个线圈都包括四匝,r.f. 励磁被施加到最靠近线圈中心点的转弯处。 离中心点第三远的转弯在用于200毫米晶圆的线圈中是不对称的。 最接近线圈中心点的两匝在用于300毫米晶圆的线圈中是不对称的。

    INTEGRATED CAPACITIVE AND INDUCTIVE POWER SOURCES FOR A PLASMA ETCHING CHAMBER
    13.
    发明申请
    INTEGRATED CAPACITIVE AND INDUCTIVE POWER SOURCES FOR A PLASMA ETCHING CHAMBER 审中-公开
    用于等离子体蚀刻室的集成电容和电感电源

    公开(公告)号:WO2007100528A3

    公开(公告)日:2008-10-23

    申请号:PCT/US2007004224

    申请日:2007-02-16

    CPC classification number: H01J37/32862 H01J37/32091 H01J37/321 H01J37/32642

    Abstract: Broadly speaking, the present invention fills these needs by providing an improved chamber cleaning mechanism. The present invention can also be used to provide additional knobs to tune the etch processes. In one embodiment, a plasma processing chamber configured to generate a plasma includes a bottom electrode assembly with an bottom electrode, wherein the bottom electrode is configured to receive a substrate. The plasma processing chamber includes a top electrode assembly with a top electrode and an inductive coil surrounding the top electrode. The inductive coil is configured to convert a gas into a plasma within a region defined within the chamber, wherein the region is outside an area defined above a top surface of the bottom electrode.

    Abstract translation: 概括地说,本发明通过提供改进的室清洁机构来满足这些需要。 本发明还可以用于提供附加的旋钮来调整蚀刻工艺。 在一个实施例中,构造成产生等离子体的等离子体处理室包括具有底部电极的底部电极组件,其中底部电极被配置为容纳衬底。 等离子体处理室包括具有顶部电极的顶部电极组件和围绕顶部电极的感应线圈。 感应线圈被配置为将气体转变成在腔室内限定的区域内的等离子体,其中该区域位于限定在底部电极的顶表面之上的区域之外。

    METHOD OF PREVENTING DAMAGE TO POROUS LOW-K MATERIALS DURING RESIST STRIPPING
    14.
    发明申请
    METHOD OF PREVENTING DAMAGE TO POROUS LOW-K MATERIALS DURING RESIST STRIPPING 审中-公开
    在耐久剥离下防止多孔低K材料损坏的方法

    公开(公告)号:WO2005060548A3

    公开(公告)日:2006-02-23

    申请号:PCT/US2004040267

    申请日:2004-12-01

    Abstract: A method of forming a feature in a porous low-K dielectric layer is provided. A porous low-K dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the porous low-K dielectric layer. A feature is etched into the porous low-K dielectric layer. A protective layer is deposited over the feature after the etching the feature. The patterned photoresist mask is stripped, so that part of the protective layer is removed, where protective walls formed from the protective layer remain in the feature.

    Abstract translation: 提供了在多孔低K电介质层中形成特征的方法。 将多孔低K电介质层放置在衬底上。 将图案化的光致抗蚀剂掩模放置在多孔低K电介质层上。 将特征蚀刻到多孔低K电介质层中。 在蚀刻特征之后,在特征上沉积保护层。 剥离图案化的光致抗蚀剂掩模,从而去除保护层的一部分,其中由保护层形成的保护壁保留在特征中。

    METHOD FOR IMPROVING UNIFORMITY AND REDUCING ETCH RATE VARIATION OF ETCHING POLYSILICON
    16.
    发明申请
    METHOD FOR IMPROVING UNIFORMITY AND REDUCING ETCH RATE VARIATION OF ETCHING POLYSILICON 审中-公开
    改善均匀性并减少蚀刻多晶硅的蚀刻速率变化的方法

    公开(公告)号:WO0175958A3

    公开(公告)日:2002-01-03

    申请号:PCT/US0108618

    申请日:2001-03-16

    CPC classification number: H01J37/32642 H01L21/32137

    Abstract: An apparatus and method for consecutively processing a series of semiconductor substrates with minimal plasma etch rate variation following cleaning with fluorine- containing gas and/or seasoning of the plasma etch chamber. The method includes steps of (a) placing a semiconductor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) etching an exposed surface of the substrate by supplying an etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively etching additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by minimizing a recombination rate of H and Br on a silicon carbide edge ring surrounding the substrate at a rate sufficient to offset a rate at which Br is consumed across the substrate. The method can be carried out using pure HBr or combination of HBr with other gases.

    Abstract translation: 一种用于在用含氟气体清洁和/或等离子体蚀刻室的调节之后以最小等离子体蚀刻速率变化连续处理一系列半导体衬底的装置和方法。 该方法包括以下步骤:(a)将半导体衬底放置在等离子体蚀刻室中的衬底支撑件上,(b)在室中保持真空,(c)通过向腔室中提供蚀刻气体来蚀刻衬底的暴露表面 并激励蚀刻气体以在腔室中形成等离子体,(d)从腔室中移除基底; 并且(e)通过重复步骤(ad)连续地蚀刻腔室中的附加衬底,蚀刻步骤通过使围绕衬底的碳化硅边缘环上的H和Br的复合速率以足以抵消速率 其中Br在基底上被消耗。 该方法可以使用纯HBr或HBr与其他气体的组合进行。

    17.
    发明专利
    未知

    公开(公告)号:DE60128229T2

    公开(公告)日:2007-08-30

    申请号:DE60128229

    申请日:2001-06-26

    Applicant: LAM RES CORP

    Abstract: 200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.

    Method for improving uniformity and reducing etch rate variation of etching polysilicon

    公开(公告)号:AU4753701A

    公开(公告)日:2001-10-15

    申请号:AU4753701

    申请日:2001-03-16

    Applicant: LAM RES CORP

    Abstract: An apparatus and method for consecutively processing a series of semiconductor substrates with minimal plasma etch rate variation following cleaning with fluorine-containing gas and/or seasoning of the plasma etch chamber. The method includes steps of (a) placing a semiconductor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) etching an exposed surface of the substrate by supplying an etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively etching additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by minimizing a recombination rate of H and Br on a silicon carbide edge ring surrounding the substrate at a rate sufficient to offset a rate at which Br is consumed across the substrate. The method can be carried out using pure HBr or combination of HBr with other gases.

    INTEGRATED CAPACITIVE AND INDUCTIVE POWER SOURCES FOR A PLASMA ETCHING CHAMBER

    公开(公告)号:SG10201405522RA

    公开(公告)日:2014-10-30

    申请号:SG10201405522R

    申请日:2007-02-16

    Applicant: LAM RES CORP

    Abstract: Broadly speaking, the embodiments of the present invention provide an improved chamber cleaning mechanism. The present invention can also be used to provide additional knobs to tune the etch processes. In one embodiment, a plasma processing chamber configured to generate a plasma includes a bottom electrode assembly with an bottom electrode, wherein the bottom electrode is configured to receive a substrate. The plasma processing chamber includes a top electrode assembly with a top electrode and an inductive coil surrounding the top electrode. The inductive coil is configured to convert a gas into a plasma within a region defined within the chamber, wherein the region is outside an area defined above a top surface of the bottom electrode.

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