中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.064 seconds)

    12.
    发明专利
    未知

    公开(公告)号：FR2806833B1

    公开(公告)日：2002-06-14

    申请号：FR0003844

    申请日：2000-03-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  HAOND MICHEL

    IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

    Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

    Fabrication of a Silicon-on-Insulator or Silicon-on-Nothing substrate for a semiconductor device involves forming a tunnel between a silicon layer and an initial substrate after defining and masking active zones and forming trenches
    14.
    发明专利
    Fabrication of a Silicon-on-Insulator or Silicon-on-Nothing substrate for a semiconductor device involves forming a tunnel between a silicon layer and an initial substrate after defining and masking active zones and forming trenches 未知

    公开(公告)号：FR2812764A1

    公开(公告)日：2002-02-08

    申请号：FR0010176

    申请日：2000-08-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  HAOND MICHEL ,  DUTARTRE DIDIER

    IPC: H01L21/762 ,  H01L21/328

    Abstract: Substrate production involves epitaxially growing semiconductor layers on an initial substrate (1), defining and masking active zones, forming spacers and trenches, lateral etching of the first epitaxial layer, filling the formed tunnel with a dielectric for a Silicon-On-Insulator (SOI) substrate or leaving void for a Silicon-On-Nothing (SON) substrate, and filling the trenches with a dielectric. Production of a SOI substrate involves: (a) epitaxial growth, in sequence, of a Ge or SiGe layer and a Si layer (3) on an initial, preferably Si, substrate; (b) defining and masking active zones; (c) forming insulating spacers (7) in trench zones around the perimeter of each active zone at predetermined intervals and back-to-back with the sides of the active zones; (d) etching the trenches; (e) lateral etching of the Ge or SiGe layer; (f) filling the formed laterally etched space (tunnel) (8) with a dielectric, preferably SiO2, or passivation of tunnel walls followed by filling the tunnel (8) with a dielectric different from SiO2; (g) filling the trenches with a dielectric, preferably SiO2; and (h) performing finishing operations. Production of a SON substrate involves the same procedure except that stage (f) is omitted and passivation of the tunnel walls can be carried out prior to filling the trenches with a dielectric. The thickness of the Ge or SiGe layer is 1-50 nm, preferably 10-30 nm, and the thickness of the Si layer (3) is 10-50 nm, preferably 5-20 nm. Following the finishing operations a 'bulk' zone is produced in the SOI or SON substrate by masking, using a resin, the region that must be retained, followed by removal of layers in the unmasked region. A multilayer of alternating Si layers (3) and Ge or SiGe layers (2) can be formed in stage (a) of the SOI or SON substrate production process. Independent claims are given for: (i) a substrate having at least one active SOI active zone surrounded by isolating trenches; and (ii) a substrate having at least one active SOI active zone surrounded by isolating trenches.

    Fabrication of MOS transistor having two gates, one being buried, includes forming semiconductor channel region transversely mounting a first gate, and forming second gate on channel region
    15.
    发明专利
    Fabrication of MOS transistor having two gates, one being buried, includes forming semiconductor channel region transversely mounting a first gate, and forming second gate on channel region 未知

    公开(公告)号：FR2806833A1

    公开(公告)日：2001-09-28

    申请号：FR0003844

    申请日：2000-03-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  HAOND MICHEL

    IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

    Abstract: MOS transistor production includes: forming first gate (2) in silicon-on-insulator substrate (1); forming semiconducting channel region transversely surmounting first gate, and drain (16) and source (17) regions respectively on each side of channel region; isolating channel region from upper surface of first gate; and forming the second gate (10) on, and transversely to, the channel region. Fabrication of a MOS transistor comprising a channel region sandwiched between a first gate (2) and a second gate (10) includes: (a) forming the first gate (2) in the body of a silicon-on-insulator (SOI) substrate (1); (b) on the upper surface of the substrate, forming by epitaxy a semiconducting channel region transversely surmounting the first gate (2), and semiconducting drain (16) and source (17) regions arranged respectively on each side of the channel region; (c) isolating the channel region from the upper surface of the first gate (2) by forming a tunnel under the channel region, and then filling it, at least partially, with a first dielectric material (8); and (d) forming the second gate (10) on the channel region and transversely to channel region, the second gate being separated from the upper surface of the channel region by a second dielectric material (8). An Independent claim is given for a MOS transistor produced by the above process. The thickness of dielectric material filling the tunnel produced in the MOS transistor is 1-50 nm, e.g. 20 nm.

    16.
    发明专利
    未知

    公开(公告)号：FR2803092A1

    公开(公告)日：2001-06-29

    申请号：FR9916488

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： TORRES JOAQUIM ,  GAYET PHILIPPE ,  HAOND MICHEL

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L23/528

    Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

    18.
    发明专利
    未知

    公开(公告)号：DE69935401D1

    公开(公告)日：2007-04-19

    申请号：DE69935401

    申请日：1999-10-01

    Applicant: ST MICROELECTRONICS SA

    Inventor： ALIEU JEROME ,  LAIR CHRISTOPHE ,  HAOND MICHEL

    IPC: H01L21/768 ,  H01L23/522

    Abstract: The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the germanium in order to form air-filled interconnect spaces.

Patent Agency Ranking