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    12.
    发明专利
    未知

    公开(公告)号：DE60025456D1

    公开(公告)日：2006-04-06

    申请号：DE60025456

    申请日：2000-09-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HOMEGALPINE

    IPC: H01L21/00 ,  H01L29/73 ,  H01L21/205 ,  H01L21/22 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

    Abstract: Bipolar transistor fabrication includes a step of producing a base region (8) comprising an extrinsic base (800) and an intrinsic base, and a step of producing an emitter block having a narrower lower part located in an emitter-window above the intrinsic base. Production of the extrinsic base (800) involves dopant implantation after defining the emitter-window, on both sides at a determined distance from the lateral limits of the emitter-window, with self-alignment about the emitter-window, and before emitter block formation. An oxide block (13) is formed on an insulating layer located above the intrinsic base. The oxide block (13) has a narrower lower part (130) located in an etched hole of the insulating layer and whose dimensions correspond to those of the emitter-window, and an upper wider part (131) resting on the insulating layer. The lateral sides of the etched hole of the insulating layer are self-aligned with the lateral sides (FV) of the upper part of the oxide block. Ion implantation of the extrinsic base is formed on both sides of the upper part of the oxide block (13).

    13.
    发明专利
    未知

    公开(公告)号：FR2848724B1

    公开(公告)日：2005-04-15

    申请号：FR0215837

    申请日：2002-12-13

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

    IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

    Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

    15.
    发明专利
    未知

    公开(公告)号：DE69808190T2

    公开(公告)日：2003-05-28

    申请号：DE69808190

    申请日：1998-07-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： JAOUEN HERVE ,  MARTY MICHEL

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L27/10 ,  H01L29/92 ,  H01L21/3205

    Abstract: Production of a metal-metal capacitor within an IC is carried out by forming the two metal electrodes (40, 71) and the dielectric layer (61) on the lower insulating layer (2) bearing a metallisation level (M1) of the IC before depositing the upper insulating layer (80) for covering the metallisation level (M1). Also claimed is an IC including a metal-metal capacitor (40, 61, 71) produced as described above. Preferably, the first capacitor electrode (40) is part of the metallisation level (preferably aluminium), the second electrode (70, 71) is a thinner layer preferably of aluminium or tungsten and the dielectric layer (61) is a thin SiO2, Si3N4 or Ta2O5 layer.

    17.
    发明专利
    未知

    公开(公告)号：FR2779573A1

    公开(公告)日：1999-12-10

    申请号：FR9807061

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  REGOLINI JORGE LUIS

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737 ,  H01L29/732

    Abstract: The bipolar transistor comprises a base (Be) of heterojunction silicon-germanium. The base is in block (8) of layers of silicon and silicon-germanium on an initial layer (17) of silicon nitride spread on a region with lateral isolation (5). An internal collector (4) is enclosed and situated inside a window in the layer of silicon nitride. The fabrication process includes the growth of a layer of silicon dioxide on a block of semiconductor. A layer of silicon nitride (Si3N4) is then deposited, and etched until the layer of silicon dioxide. A chemical process is used to remove a portion of the layer of silicon dioxide within the window. The layer of silicon nitride has a thickness of about 300 Angstrom, and that of silicon dioxide about 200 Angstrom.

    18.
    发明专利
    未知

    公开(公告)号：FR2779572A1

    公开(公告)日：1999-12-10

    申请号：FR9807059

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

    Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

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