公开(公告)号：FR2846795A1

公开(公告)日：2004-05-07

申请号：FR0213838

申请日：2002-11-05

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  VILLARET ALEXANDRE ,  SKOTNICKI THOMAS

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A integrated memory circuit comprises at least one memory cell formed from a single transistor of which the gate (GR) possesses a lower surface insulated from the channel region (RC) by an insulation layer (CIS) incorporating a succession of potential pits (ND) essentially arranged at a distance from the gate and the channel region in a plane essentially parallel to the lower surface of the gate and these potential pits are able to contain an electric charge confined in the plane and displaceable on command in the plane towards a first confinement region close to the source region (RS) or towards a second confinement region close to the drain region (RD), in a manner to define two memory states for the cell. Independent claims are also included for: (a) a method for the memorisation of binary data in the memory cell of this integrated memory circuit; (b) a method for the manufacture of this integrated memory circuit.

公开(公告)号：FR2828763B1

公开(公告)日：2004-01-16

申请号：FR0110867

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  CAILLAT CHRISTIAN

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: Integrated circuit with dram memory cell Integrated circuit comprising a substrate (1), at least one capacitor (9) placed above the substrate (1) and provided with a first electrode (5), with a second electrode (8) and with a dielectric (7) placed between the two electrodes, at least one via for connection between the substrate (1) and a conductor level lying above the capacitor (9), and a dielectric covering the substrate (1) and surrounding both the capacitor (9) and the via (6). The via comprises a first portion (18) lying between the substrate and the lower level of the first electrode, a second portion (6) lying between the lower level of the first electrode and the upper level of the first electrode, and a third portion (12) in contact with the first portion and flush with the said conductor level, the second portion being made from the same material as the first electrode of the capacitor.

公开(公告)号：FR2824423B1

公开(公告)日：2003-09-05

申请号：FR0105881

申请日：2001-05-02

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  CAILLAT CHRISTIAN

IPC: H01L21/02 ,  H01L21/314 ,  H01L23/522 ,  H01L21/71 ,  H01L21/768

公开(公告)号：FR2828766A1

公开(公告)日：2003-02-21

申请号：FR0110866

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L23/498 ,  H01L21/60

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

公开(公告)号：FR2828763A1

公开(公告)日：2003-02-21

申请号：FR0110867

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  CAILLAT CHRISTIAN

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: The invention concerns an integrated circuit comprising a substrate (1), at least a capacitor (9) arranged above the substrate (1) and provided with a first electrode (5), a second electrode (8), and a dielectric (7) arranged between the two electrodes, at least a connecting feedthrough between the substrate (1) and a conductive level located above the capacitor (9), and a dielectric material covering the substrate (1) and enclosing the capacitor (9) and the feedthrough. The feedthrough comprises a first portion (18) arranged between the substrate and the lower level of the first electrode, a second portion (6) arranged between the lower level of the first electrode and the upper level of the first electrode, and a third portion (12) in contact with the first electrode and flush with said conductive level, the second portion being made of the same material as the first electrode of the capacitor.

公开(公告)号：FR2969392A1

公开(公告)日：2012-06-22

申请号：FR1060638

申请日：2010-12-16

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： MAZOYER PASCALE ,  HALIMAOUI AOMAR

IPC: H01M2/02 ,  H01M8/16

Abstract: Boîtier, comprenant un corps (1) comportant un premier élément (10) en silicium et un deuxième élément (20) en silicium poreux, au moins une première cavité (31) ménagée dans le silicium poreux, une première zone de contact électriquement conductrice (41) électriquement couplée à au moins une partie (310) d'au moins une paroi interne de ladite au moins une première cavité (31), une deuxième zone de contact électriquement conductrice (42) électriquement couplée à une portion (320) dudit deuxième élément (20) différente des parois internes de ladite au moins une première cavité (31), les deux zones de contact (41, 42) étant mutuellement électriquement isolées.

公开(公告)号：FR2930371B1

公开(公告)日：2010-10-29

申请号：FR0802106

申请日：2008-04-16

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  BOSSU GERMAIN

IPC: H01L21/8239 ,  G11C11/34 ,  G11C16/02

公开(公告)号：FR2830365B1

公开(公告)日：2004-12-24

申请号：FR0112519

申请日：2001-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  MAZOYER PASCALE ,  FAZAN PIERRE

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.

公开(公告)号：FR2828766B1

公开(公告)日：2004-01-16

申请号：FR0110866

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L23/498 ,  H01L21/60

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

公开(公告)号：FR2830365A1

公开(公告)日：2003-04-04

申请号：FR0112519

申请日：2001-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  MAZOYER PASCALE ,  FAZAN PIERRE

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.