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公开(公告)号：DE69625192D1
公开(公告)日：2003-01-16
申请号：DE69625192
申请日：1996-08-07
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , DEMICHELI MARCO , DEMICHELI DAVIDE , PATTI GIUSEPPE
Abstract: A servo-demodulator for a pair of alternating signals generated by a magnetic disc read head and indicative of the position of the read head in relation to the centre of a recorded track, comprising a peak detector (5) for successively and individually sampling the amplitude of each of a plurality of peaks of the said pair of alternating signals, and a capacitor (9) periodically connected to the output of the peak detector (5) by a control logic (7) for deriving a weighted average of the various successively sampled amplitudes, obtaining an averaged measure of amplitude with high immunity to noise.
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公开(公告)号：DE69614501D1
公开(公告)日：2001-09-20
申请号：DE69614501
申请日：1996-03-08
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PISATI VALERIO
Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.
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公开(公告)号：DE69812369T2
公开(公告)日：2004-02-19
申请号：DE69812369
申请日：1998-12-01
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , DEMICHELI MARCO , OTTINI DANIELE , SAVO ALESSANDRO
Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.
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公开(公告)号：IT1316796B1
公开(公告)日：2003-05-12
申请号：ITMI20000469
申请日：2000-03-09
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , DEMICHELI MARCO , BRUCCOLERI MELCHIORRE
Abstract: A circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, including at least one differential cell multiplier whose cell includes a pair of input MOS transistors having respective conduction terminals linked together at a circuit node. Advantageously, provided in parallel with each of the cell input transistors, are a plurality of transistors individually connectable to and disconnectable from each of the input transistors by corresponding switches.
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公开(公告)号：DE69529615D1
公开(公告)日：2003-03-20
申请号：DE69529615
申请日：1995-11-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , CUSINATO PAOLO
Abstract: A timed bistable circuit (latch) is described which includes two inverters (INV1, INV2) each having its input (Z+, Z-) connected to the output of the other, an output (U-, U+) of the circuit via a "buffer" (BF2, BF1) and an input (I+, I-) of the circuit via a controlled electronic switch (S1, S2). The supply terminals (A, B) of the inverters are connected to the supply terminals (Vdd, GND) of the circuit via another two controlled switches (S3, S4). A clock generator (CK') provides timing signals (Vck, Vck) to control both the input switches (S1, S2) to open or close and to control the supply switches (S3, S4) to close or open when the input switches (S1, S2) are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches (S5, S6) between the supply terminals (A, B) of the inverters and the supply terminals (Vdd, GND) which are controlled by a timing signal (Vckd) in such a way as to close with a predetermined delay with respect to the closure of the input switches (S1, S2) and to open when these latter open.
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Patent Agency Ranking
公开(公告)号：DE69426776T2
公开(公告)日：2001-06-13
申请号：DE69426776
申请日：1994-12-27
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PORTALURI SALVATORE
Abstract: The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.
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公开(公告)号：ITTO20010538D0
公开(公告)日：2001-06-05
申请号：ITTO20010538
申请日：2001-06-05
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , BASCHIROTTO ANDREA , CUSINATO PAOLO
IPC: H03F3/45
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公开(公告)号：ITMI20000469D0
公开(公告)日：2000-03-09
申请号：ITMI20000469
申请日：2000-03-09
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , PISATI VALERIO , DEMICHELI MARCO
Abstract: A circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, including at least one differential cell multiplier whose cell includes a pair of input MOS transistors having respective conduction terminals linked together at a circuit node. Advantageously, provided in parallel with each of the cell input transistors, are a plurality of transistors individually connectable to and disconnectable from each of the input transistors by corresponding switches.
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公开(公告)号：DE69833932D1
公开(公告)日：2006-05-11
申请号：DE69833932
申请日：1998-04-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , OTTINI DANIELE , DEMICHELI MARCO , BOLLATI GIACOMINO
Abstract: A full-wave rectifier for monitoring the amplitude of a differential analog signal (IN+, IN-) is composed of a differential Track&Hold stage (T&H) controlled by a first differential logic timing signal (TClk+, TClk-), tracking the differential analog input signal (IN+, IN-) during a tracking phase that corresponds to a high logic stage of the first differential timing signal (TClk+, TClk-), producing a differential output signal that is a replica of the input signal and storing it during a successive storing phase that corresponds to a low logic state of the first differential timing signal (TClk+, TClk-); a first differential output amplifier ( @ ) having inputs coupled to the output of the Track&Hold stage (T&H); a differential bistable circuit (LATCH-ECL), controlled by a second differential logic timing signal (DClk+, DClk-), having inputs coupled to the differential outputs of the first amplifier ( @ ) and producing a third differential logic control signal (S+, S-); a second multiplexed amplifier (Analog-Amp @ ), controlled by the third differential control signal (S+, S-), having inputs coupled to the output of the Track&Hold stage (T&H) and outputting a differential analog signal (OUT+, OUT-) of amplitude function of the amplitude of the differential input signal (IN+, IN-); a timing circuit (T @ C @ ) receiving at an input a differential logic synchronism signal (Clk+, Clk-) and generating the first differential timing signal (TClk+, TClk-) of said Track&Hold stage (T&H) and the second differential timing signal (DClk+, DClk-) of said bistable circuit (LATCH-ECL).
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公开(公告)号：DE69825250D1
公开(公告)日：2004-09-02
申请号：DE69825250
申请日：1998-05-15
Applicant: ST MICROELECTRONICS SRL
Inventor： DE MICHELI MARCO , PORTALURI SALVATORE , BOLLATI GIACOMINO , BRUCCOLERI MELCHIORRE
Abstract: A transconductance control circuit, particularly for a continuous-time filter, comprising a transconductor (4) across which a constant voltage is input; the transconductor is connected to a DAC (7) to set a reference current (IR); a feedback loop (9, 10, 23, 11) is provided between the output of the transconductor (4) and its input; the particularity of the circuit is the fact that it further comprises means (20, 22, 24) for mirroring the reference current (IR) set by the DAC (7) which are suitable to mirror the current both to the feedback loop and to at least one cell of a filter which is cascade-connected.
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