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    12.
    发明专利
    未知

    公开(公告)号：DE69631657D1

    公开(公告)日：2004-04-01

    申请号：DE69631657

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  ROLANDI PIER LUIGI ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  SABATINI MARCO

    IPC: G06G7/26 ,  G06N3/063 ,  G11C16/04 ,  G06G7/60

    Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors (M1,M2) having source and drain terminals which are coupled together and to an injection node (ND), and at least one corresponding pair of generators (G1,G2) of substantially step-like voltage signals (S1,S2) having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors (M1,M2); the signal generators (G1,G2) being such that the initial value of a first (S1) of the signals is substantially the equal of the final value of a second (S2) of the signals, and that the final value of the first signal (S1) is substantially the equal of the initial value of the second signal (S2).

    13.
    发明专利
    未知

    公开(公告)号：DE69628753D1

    公开(公告)日：2003-07-24

    申请号：DE69628753

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

    IPC: G11C15/00 ,  G11C15/04

    Abstract: An input structure (1) for associative memories, including an array of elementary cells (2), a number of input lines (20), a number of output lines (30), a number of address lines (40), and a number of enabling lines (50). Each elementary cell (2) is formed by a D type latch (3) having a data input connected to one of the address lines (40) and an enabling input connected to one of the enabling lines (50), and by a switch (4) connected between an input line and an output line, and having a control input connected to the output of a respective latch to selectively connect the respective input line (20) and output line (30) according to the data stored in the latch.

    14.
    发明专利
    未知

    公开(公告)号：DE69721252D1

    公开(公告)日：2003-05-28

    申请号：DE69721252

    申请日：1997-09-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  CANEGALLO ROBERTO ,  CHIOFFI ERNESTINA ,  GERNA DANILO ,  ROLANDI PIER LUIGI

    IPC: G11C27/00

    Abstract: Device for analog programming comprising a current mirror circuit (19) connected to the drain terminals of a cell to be programmed (2) and of a MOS reference transistor (27); an operational amplifier (31) having inputs connected to the drain terminals (13) of the cell (2) and respectively of the MOS transistor (27) and output connected to the control terminal (30) of the MOS transistor. During programming, the control and drain terminals of the cell (2) are biased at corresponding programming voltages and the output voltage of the operational amplifier (31), which is correlated to the current threshold voltage level of the cell (2), is monitored and the programming is interrupted when this output voltage becomes at least equal to a reference voltage correlated to the threshold value desired for the cell.

    16.
    发明专利
    未知

    公开(公告)号：IT1303201B1

    公开(公告)日：2000-10-30

    申请号：ITTO980990

    申请日：1998-11-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANEGALLO ROBERTO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C16/12

    Abstract: A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.

    20.
    发明专利
    未知

    公开(公告)号：DE60027706T2

    公开(公告)日：2007-04-26

    申请号：DE60027706

    申请日：2000-02-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZANUCCOLI MAURO ,  CANEGALLO ROBERTO ,  DOZZA DAVIDE

    IPC: H02M3/07

    Abstract: The load pump booster device (1) with transfer and recovery of the charge comprises a charge pump circuit (2) with an output terminal (30.N) which is connected to a load capacitor (12) by means of a load node (50). In turn, the charge pump circuit (2) comprises a plurality of transfer transistors (15.0, ..., 15.j, ..., 15.N) which are connected to one another in series, and define a plurality of transfer nodes (30.0, ..., 30.j, ..., 30.N). Each transfer node (30.0, ..., 30.j, ..., 30.N) is connected to a storage capacitor (14.0, ..., 14.j, ..., 14.N). The booster device (1) also comprises a plurality of controlled switches (40.0, ..., 40.j, ..., 40.N) which are interposed between the said load node (50) and a respective transfer node (30.0, ..., 30.j, ..., 30.N), in order to connect to the said load node (50) a single one of the said transfer nodes (30.0, ..., 30.j, ..., 30.N). By this means, between the load capacitor (12) and the storage capacitors (14.0, ..., 14.j, ..., 14.N) there takes place a phase of transfer of charge followed by a phase of recovery of charge, from the storage capacitors (14.0, ..., 14.j, ..., 14.N) to the load capacitor (12).

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