公开(公告)号：WO2008026228A8

公开(公告)日：2008-07-03

申请号：PCT/IT2006000629

申请日：2006-08-28

Applicant: ST MICROELECTRONICS SRL ,  ZAMPROGNO MARCO ,  CONFALONIERI PIERANGELO ,  MINUTI ALBERTO

Inventor： ZAMPROGNO MARCO ,  CONFALONIERI PIERANGELO ,  MINUTI ALBERTO

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN") input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

Abstract translation: 一种用于从差分到单端转换的电路（1），包括：具有第一（IN +）和第二（IN“）输入的差分放大级（2）;第一（5）和不同的第二 分别与转换电路（1）的输出（OUT *）和辅助输出（AUXOUT *）可操作地耦合的差分级的充电电路（6），该电路还包括第一（7） 以及第二缓冲电路，每个功能地布置在所述输出之一和所述充电电路中的一个之间，缓冲电路被配置为最小化所述输出（OUT *，AUXOUT * ）。

公开(公告)号：DE602004007101D1

公开(公告)日：2007-08-02

申请号：DE602004007101

申请日：2004-04-01

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI PIERANGELO ,  ZAMPROGNO MARCO ,  GIRARDI FRANCESCA

IPC: H03M1/46 ,  H03M1/00

公开(公告)号：DE69915251D1

公开(公告)日：2004-04-08

申请号：DE69915251

申请日：1999-03-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI PIERANGELO ,  NAGARI ANGELO ,  MECCHIA ALESSANDRO

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

Abstract: A set (Array_SAR) of sampling capacitors weighted according to a binary code is charged through a first capacitive unit (Array_Vin), whose capacitance is equal to the sum of the capacitances of the set (Array_SAR), at a voltage Vcm-Vin/2. The conversion is carried out by the SAR process by means of a comparator (13') and a logic unit (14') which operates the switches (SW1'-SW6') associated with the capacitors. The final position of the switches is loaded into a register (15') which supplies the digital output signal (Nout). To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units (Array_-Vref) and (Array_GND) are provided, with the same capacitance as the first capacitive unit, and these make it possible to present all the disturbances at the input of the comparator (13') in common mode and therefore without any effect on the output (OutCmp).

公开(公告)号：ITRM20010407A1

公开(公告)日：2003-01-10

申请号：ITRM20010407

申请日：2001-07-10

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI PIERANGELO ,  ZAMPROGNO MARCO ,  NAGARI ANGELO

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

公开(公告)号：DE69517693T2

公开(公告)日：2001-03-01

申请号：DE69517693

申请日：1995-12-29

Applicant: ST MICROELECTRONICS SRL

Inventor： DALLAVALLE CARLO ,  CONFALONIERI PIERANGELO

IPC: H01L27/02 ,  H01L23/00

Abstract: A cell library for the design of integrated circuits, for example using CMOS technology, is described. The cells define circuit modules (11) in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips (12, 13; 12, 14) for connection to the supply (Vcc, Vss), at least one of which is in contact (12p, 13n; 14n) with the source regions (4, 5) of MOS transistors of the CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library described also provides a group (1) of cells in which there is provided at least one additional trace which defines an additional strip (15) for connection to the outside (Vb) which is in contact (15s) with the body regions of the MOS transistors of the CMOS pair.

公开(公告)号：DE69424668T2

公开(公告)日：2001-01-25

申请号：DE69424668

申请日：1994-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO

IPC: H01L27/04 ,  H01L21/822 ,  H02M3/07 ,  H02M3/00

Abstract: An output voltage stabilisation circuit for a voltage multiplier of the type comprising a first charge transfer capacitor (C1) designed to take and transfer electrical charges from the input terminal (IN) to the output terminal (OUT) of a second capacitor (C2) for charge storage connected between the output terminal (OUT) and ground comprises an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage (Vrif) and the output voltage (Vout) of the voltage multiplier and said continuous voltage is applied to one terminal of said charge transfer capacitor (C1).

公开(公告)号：DE69413814T2

公开(公告)日：1999-02-25

申请号：DE69413814

申请日：1994-07-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687

Abstract: MOS-transistor switch without body effect comprising a pair of p-channel transistors (M1, M2) inserted in series between two connection terminals (A, B) and a third transistor (M3) with n-channel which is inserted between a connection node of the pair and a minimum potential reference (VSS) and a fourth transistor (M4) with n-channel in parallel with the pair of transistors (M1, M2). The substrates of the transistors of the pair are connected to the connection terminals (A, B). The substrate both of the third transistor (M3) and the fourth transistor (M4) is connected to the potential reference (VSS).

公开(公告)号：DE69411368T2

公开(公告)日：1998-10-22

申请号：DE69411368

申请日：1994-05-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CONFALONIERI PIERANGELO

IPC: H01L27/04 ,  G06F11/00 ,  G11C5/00 ,  G11C7/10 ,  H01L21/82 ,  H01L21/822 ,  H01L27/07 ,  H03K19/173 ,  H01L23/525

公开(公告)号：DE69226021T2

公开(公告)日：1998-10-22

申请号：DE69226021

申请日：1992-09-23

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CONFALONIERI PIERANGELO

IPC: H03K17/06 ,  H03K17/687

Abstract: A driver circuit for an electronic switch (2) which is to be operated from a clock signal (F) having a predetermined frequency, comprises an input pin (A) being applied the clock signal, and a voltage doubler (1) connected between said pin (A) and the switch (2).

公开(公告)号：DE69316880D1

公开(公告)日：1998-03-12

申请号：DE69316880

申请日：1993-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： DALLAVALLE CARLO ,  CRIPPA CARLO ,  CONFALONIERI PIERANGELO

IPC: H03G3/20 ,  H03G3/30 ,  H03G5/16

Abstract: A digital circuit for controlling the gain of an amplifier stage (FA) of a coded signal receiving channel (1) comprising a peak detector (2) coupled to the input terminal of the receiving channel through a coded signal rectifying circuit means, and a gain control stage (3) comprising a digital comparator (6) having two input terminals respectively connected to an output terminal of the peak detecctor and to a memory (8), and an output terminal coupled to a gain control terminal of the amplifier stage and to address select terminals of the memory containing predetermined peak values in coded form.