公开(公告)号：EP1296361A1

公开(公告)日：2003-03-26

申请号：EP01830580.5

申请日：2001-09-13

Applicant: STMicroelectronics S.r.l.

Inventor： Ward, Peter ,  Ferla, Giuseppe ,  Lorenti, Simona

IPC: H01L21/20

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/2022

Abstract: A process of forming an interface free layer of silicon on a substrate of monocrystalline silicon (105) including the steps of: providing a substrate of monocrystalline silicon (105) having a surface substantially free of oxide, depositing a layer of silicon in-situ doped (120) on the surface of the substrate in an oxygen-free environment and at a temperature below 700°C for obtaining a first monocrystalline portion (120m) of the silicon layer adjacent to the substrate and a second polycrystalline portion (120p) of the silicon layer spaced apart from the substrate, and heating the layer of silicon for growing the monocrystalline portion through part of the polycrystalline portion.

Abstract translation: 具有基本上不含氧化物沉积硅原位掺杂的层的表面上提供的单晶硅衬底（105）：在硅的界面自由层的单晶硅（105）的在基板上形成包括以下步骤的方法 在无氧环境，并在低于700℃的温度下，用于获得所述硅层的第一单晶部分（120米）毗邻的基板和一个第二多晶部分（120P）的基板的表面上（120） 硅层从衬底隔开，以及用于通过所述多晶部分的一部分生长单晶部分加热硅的层。

公开(公告)号：EP1278234A2

公开(公告)日：2003-01-22

申请号：EP01127923.9

申请日：2001-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Cerofolini, Gianfranco ,  Ferla, Giuseppe

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/312

CPC classification number: H01L21/28167 ,  H01L29/51

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer (3) formed between two silicon plates (1,2), and wherein the silicon plates (1,2) overhang the oxide layer (3) all around to define an undercut (5) having a substantially rectangular cross-sectional shape.
The method comprises the steps of:

chemically altering the surfaces of the silicon plates (1,2) to have different functional groups (6,7) provided in the undercut (5) from those in the remainder of the surfaces; and
selectively reacting the functional groups (6,7) provided in the undercut (5) with an organic molecule (8) having a reversibly reducible center and a molecular length substantially equal to the width of the undercut (5), thereby to establish a covalent bond to each end of the organic molecule (8).

Abstract translation: 公开了一种通过电介质栅极氧化物制造具有可控和可调制传导路径的MOS晶体管的方法，其中晶体管结构包括形成在两个硅板（1,2）之间的电介质氧化物层（3），并且其中硅板 （1,2）围绕所述氧化物层（3）突出以限定具有基本上矩形横截面形状的底切（5）。 该方法包括以下步骤：化学改变硅板（1,2）的表面以具有设置在底切（5）中的不同的官能团（6,7）与其余表面中的那些; 选择性地使底切（5）中提供的官能团（6,7）与具有可逆可还原中心和分子长度基本上等于底切（5）的宽度的有机分子（8）反应，从而建立 与有机分子（8）的每个末端共价键。

公开(公告)号：EP1058318A1

公开(公告)日：2000-12-06

申请号：EP99830339.0

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Antonino ,  Grimaldi, Antonio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/41 ,  H01L29/06

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7811

Abstract: Semiconductor device for high voltages comprising at least one power component (21), e.g. a power MOSFET, and at least one edge termination (100). Said edge termination (100) comprises a voltage divider including a plurality of diode-connected MOS transistors (31;32;33;34) in series, said edge termination (100) being connected between current-carrying, main terminals of said power component (21).

Abstract translation: 用于高电压的半导体器件包括至少一个功率部件（21），例如， 功率MOSFET和至少一个边缘终端（100）。 所述边缘终端（100）包括一个分压器，包括串联的多个二极管连接的MOS晶体管（31; 32; 33; 34），所述边缘终端（100）连接在所述功率部件的载流主端子 （21）。

公开(公告)号：EP0443297B1

公开(公告)日：1999-09-01

申请号：EP90830063.5

申请日：1990-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Santangelo, Antonello ,  Magro, Carmelo ,  Ferla, Giuseppe ,  Lanza, Paolo

IPC: H01L21/285 ,  H01L21/60

CPC classification number: H01L29/66166 ,  H01L21/28518 ,  H01L21/76879

公开(公告)号：EP1058318B1

公开(公告)日：2008-04-16

申请号：EP99830339.0

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Antonino ,  Grimaldi, Antonio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/41 ,  H01L29/06

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7811

公开(公告)号：EP1659638A1

公开(公告)日：2006-05-24

申请号：EP05025288.1

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712

Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors (2) having respective gate structures (12) and comprising a gate oxide (7) with double thickness having a thick central part (8) and lateral portions (9) of reduced thickness. Such device exhibiting gate structures (12) comprising first gate conductive portions (13) overlapped onto said lateral portions (9) of reduced thickness to define, for the elementary Mos transistors (2), the gate electrodes, as well as a conductive structure or mesh (14). Such conductive structure (14) comprising a plurality of second conductive portions (15) overlapped onto the thick central part (8) of gate oxide (7) and interconnected to each other and to the first gate conductive portions (13) by means of a plurality of conducive bridges (16). The present invention further relates to a method for realising the power MOS device.

Abstract translation: 该功率MOS器件包括具有各自的栅极结构（12）的多个基本功率MOS晶体管（2），并且包括具有厚度为中心部分（8）的厚度的双层厚度的栅极氧化物（7）和侧壁部分 减小厚度。 这种具有栅极结构（12）的器件包括第一栅极导电部分（13），该第一栅极导电部分重叠在所述侧面部分（9）上以减小厚度，以限定基本的MOS晶体管（2），栅极电极以及导电结构 网格（14）。 这种导电结构（14）包括多个第二导电部分（15），其重叠在栅极氧化物（7）的厚的中心部分（8）上并且通过一个第二栅极导电部分（13）彼此互连并连接到第一栅极导电部分 多个有利桥梁（16）。 本发明还涉及实现功率MOS器件的方法。

公开(公告)号：EP1014565B1

公开(公告)日：2006-05-10

申请号：EP98830772.4

申请日：1998-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Palmisano, Giuseppe ,  Ferla, Giuseppe ,  Girlando, Giovanni

IPC: H03F1/56 ,  H03F1/22

CPC classification number: H03F1/22 ,  H03F1/565 ,  H03F2200/294 ,  H03F2200/372

公开(公告)号：EP1643558A1

公开(公告)日：2006-04-05

申请号：EP04425733.5

申请日：2004-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferrucio ,  Ferla, Giuseppe ,  Magri', Angelo

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

Abstract: A vertical conduction electronic power device and corresponding realisation method, the device being integrated on a semiconductor substrate (10) and comprising respective gate (20), source (25) and drain (30) areas, realised in an epitaxial layer (40) arranged on said semiconductor substrate (10) and comprising respective gate (21), source (26) and drain (31) metallisations realised by means of a first metallisation level as well as gate (60), source and drain (70) terminals or pads realised by means of a second metallisation level. The device is configured as a set of modular areas (100) extending parallel to each other, each having a rectangular elongate source area (25) perimetrically surrounded by a narrow gate area (20), and separated from each other by regions (30a) with drain area (30) extending parallel and connected at the opposite ends thereof to a second closed region (30b) with drain area (30) forming a device outer peripheral edge; as well as a sinker structure (45) extending perpendicularly to the substrate and formed by a grid of sinker (S) located below both the first parallel regions (30a) and the second closed region (30b) with drain area (30) in order to favour a conductive channel for a current coming from the source area (25) and directed towards the drain area (30) across the substrate (10).

Abstract translation: 一种垂直传导电子功率器件及相应的实现方法，该器件集成在半导体衬底（10）上并且包括在外延层（40）中实现的相应的栅极（20），源极（25）和漏极（30） 在所述半导体衬底（10）上并且包括相应的栅极（21），借助于第一金属化级别实现的源极（26）和漏极（31），以及栅极（60），源极和漏极（70）端子或焊盘 通过第二金属化水平实现。 该装置被配置为一组彼此平行延伸的模块化区域（100），每组具有由狭窄的栅极区域（20）围绕周边的矩形细长的源区域（25），并且由区域（30a）彼此分离， 其中漏区30在其相对端平行延伸并连接到具有形成器件外周边缘的漏区（30）的第二闭合区（30b）; 以及垂直于衬底延伸并由位于两个第一平行区域（30a）和第二闭合区域（30b）下方的沉降片（S）的栅格形成的沉降片结构（45），排列区域（30）依次排列有排水区域 有利于来自源极区域（25）的电流的导电通道，并且穿过衬底（10）引导到漏极区域（30）。

公开(公告)号：EP1217652A1

公开(公告)日：2002-06-26

申请号：EP00830834.8

申请日：2000-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Camalleri, Cateno Marco ,  Lorenti, Simona ,  Cali', Denise ,  Vasquez, Patrizia ,  Ferla, Giuseppe

IPC: H01L21/331 ,  H01L29/73

CPC classification number: H01L29/66272 ,  H01L21/2256 ,  H01L29/7311

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon consists in carrying out, after having loaded the wafer inside the heated chamber of the reactorand evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally comprised between 500 and 1200°C and at a vacuum generally comprised between 0.1 Pa and 60000 Pa, and preferably at a temperature of 850°C ± 15°C and at a vacuum of 11000 Pa ± 2000 Pa, for a time generally comprised between 0.1 and 120 minutes, and most preferably between 0.5 and 1.5 minutes, in order to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux.
After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally comprised between 700 and 1000°C with nitrogen protoxide (N 2 O) for a time generally comprised between 0.1 and 120 minutes, preferably between 0.5 and 1.5 minutes.
The treatment with nitrogen protoxide (N 2 O) at such a vacuum and temperature conditions causes a relatively slow oxidation of the monocrystalline silicon and allows an effective control of the amount of oxygen at the interface and a great uniformity of distribution of it on the surface. The tunnel barrier characteristics in respect to the holes of the so created oxide film at the interface between the monocrystalline silicon and the polysilicon layer show an outstanding reproducibility.

Abstract translation: 在多晶硅和单晶硅之间的界面处控制键合氧原子的分布的数量和均匀性的方法包括在将晶片装入反应器的加热室内并在氮气下抽空LPCVD反应器的腔室 气氛中，在通常为500-1200℃的温度下，通常在0.1Pa和60000Pa之间的温度下，优选在850℃±15℃的温度下，用氢处理晶片， 真空度为11000Pa +/- 2000Pa，时间通常为0.1至120分钟，最优选为0.5至1.5分钟，以除去可能与表面上的硅组合的任何和全部氧 的单晶硅在反应器的加热室内加载期间即使在氮气通量下进行。 在这样的氢处理之后，基本上在相同的真空条件下和通常在700-1000℃的温度下用氮氧化丙烷（N 2 O）进行另外的处理，时间通常在0.1至120分钟之间，优选在0.5至 1.5分钟。 在这样的真空和温度条件下用氮氧化物（N 2 O）处理导致单晶硅的相对缓慢的氧化，并且允许有效地控制界面处的氧量并且在表面上具有很大的均匀分布。 相对于在单晶硅与多晶硅层之间的界面处所形成的氧化膜的孔的隧道势垒特性显示出突出的再现性。

公开(公告)号：EP0782201B1

公开(公告)日：2000-08-30

申请号：EP95830542.7

申请日：1995-12-28

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L29/417 ,  H01L23/482 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41725 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a semiconductor material layer (3) of a first conductivity type. The elementary functional units comprise body stripes (9;90) of a second conductivity type extending substantially parallely to each other and source regions (14;140) of the first conductivity type. A conductive gate layer (17;170) is insulatively disposed over the semiconductor material layer (3) between the body stripes (9;90). A mesh (4;40) of the second conductivity type is formed in the semiconductor material layer (3) and comprises an annular frame region (5;50) surrounding the plurality of body stripes (9;90) and at least one first elongated stripe (7;60) extending within the annular frame region (5;50) in a direction substantially orthogonal to the body stripes (9;90) and merged with the annular frame region (5;50), the body stripes (9;90) being divided by the first elongated stripe (7;60) in two respective groups and being merged with the mesh (4;40). A conductive gate finger (25;250) connected to said conductive gate layer (17;170) insulatively extends over the first elongated stripe (7;60). Source metal plates (20;200) are provided covering each group of parallel body stripes and contacting each body stripe of the group. The conductive gate finger (25;250) is covered and contacted by a respective metal gate finger (27;270).