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公开(公告)号：KR1020070059857A
公开(公告)日：2007-06-12
申请号：KR1020060050320
申请日：2006-06-05
Applicant: 한국전자통신연구원
IPC: H03M3/04
CPC classification number: H03M3/50 , H03M2201/61 , H03M2201/6372 , H03M2201/8152
Abstract: A multi-bit sigma delta modulator with one DAC capacitor and a DAC(Digital-Analog Converter) for the multi-bit sigma delta modulator are provided to increase the number of output levels of the DAC by expanding the DAC capacitor. A multi-bit sigma delta modulator includes an operation amplifier(21), a sampling capacitor(22), an integration capacitor(23), a DAC capacitor(24), switches(25,26,27), and a switching controller(28). The sampling capacitor(22) is connected between the first switch(26) and an input terminal of the operation amplifier(21). The first switch(26) is connected between the input terminal of the operation amplifier(21) and a ground. The second switch(27) is connected between an input(IN) and the sampling capacitor(22). The integration capacitor(23) connects an output(OUT) and the input terminal of the operation amplifier(21) to form a negative feedback loop. The DAC capacitor(24) is connected between the DAC switch(25) and the input terminal of the operation amplifier(21). The DAC switch(25) connects reference voltages(Vrefp,Vcm,Vrefn) to the DAC capacitor(24) for a DAC of a switched capacitor structure to perform a desired operation. The switching controller(28) controls operation of the DAC switch(25) by generating a control signal according to an ADC output code of a modulator.
Abstract translation: 提供具有一个DAC电容器的多位Σ-Δ调制器和用于多位Σ-Δ调制器的DAC（数模转换器），以通过扩展DAC电容器来增加DAC的输出电平数量。 多位Σ-Δ调制器包括运算放大器（21），采样电容器（22），积分电容器（23），DAC电容器（24），开关（25,26,27）和开关控制器 28）。 采样电容器（22）连接在第一开关（26）和运算放大器（21）的输入端子之间。 第一开关（26）连接在运算放大器（21）的输入端和地之间。 第二开关（27）连接在输入（IN）和采样电容器（22）之间。 积分电容器（23）连接输出（OUT）和运算放大器（21）的输入端，以形成负反馈回路。 DAC电容器（24）连接在DAC开关（25）和运算放大器（21）的输入端子之间。 DAC开关（25）将用于开关电容器结构的DAC的参考电压（Vrefp，Vcm，Vrefn）连接到DAC电容器（24）以执行期望的操作。 开关控制器（28）通过根据调制器的ADC输出代码产生控制信号来控制DAC开关（25）的操作。
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公开(公告)号：KR101810490B1
公开(公告)日：2017-12-20
申请号：KR1020160121385
申请日：2016-09-22
Applicant: 충북대학교 산학협력단
CPC classification number: H03M1/38 , H03M1/466 , H03M2201/2233 , H03M2201/6107 , H03M2201/8152
Abstract: 본발명은기본크기의브릿지커패시터를가진분리형연속근사아날로그디지털변환기및 이의동작방법에관한것으로서, 아날로그입력전압및 기준전압을수신하고이에응답하여제1 및제2 레벨전압을생성하는아날로그디지털변환기, 상기아날로그디지털변환기로부터제1 및제2 레벨전압을수신하고이들의크기를비교하고, 논리하이(logic high) 또는논리로우(logic low)의비교신호를출력하는비교기, 및상기비교기로부터제공되는비교신호를수신하고이를이용하여디지털비트들의값을결정하는제어로직을포함하여, 연속되는비트열에대응하는아날로그신호를디지털신호로변환하는연속근사아날로그디지털변환기로서, 상기비트열의하위비트를결정하는부분및 상위비트를결정하는부분을브릿지커패시터및 브릿지스위치를통해분리시키고각각의분리된영역에서하위비트및 상위비트를결정함으로써, 브릿지커패시터를기본적인커패시터사이즈(1C)로만들어서정확히구현이가능하며, 추가적인보정회로없이하위비트에서의정확도를향상시킨다.
Abstract translation: 本发明涉及一种分离型逐次逼近模拟 - 数字转换器和操作方法与基本尺寸时，模拟输入电压和所述模拟数字转换器，用于响应于该接收参考电压并产生第一mitje第二电平电压的桥路电容上，则 接收由所述比较器提供比较信号，并且比较器输出一个第一比较信号mitje第二电平电压，用于比较接收到的幅度和此，逻辑高（逻辑高电平），或从模拟数字转换器逻辑低（逻辑低） 并且通过使用这一点，用于确定所述数字位的值的控制逻辑中，对应于一个列的模拟信号的连续比特作为逐次逼近模拟 - 数字转换器，用于转换一个数字信号，该部分与确定的比特序列低位比特的高位比特 由一个桥式电容器和一个桥式开关以及较低位分开 通过确定上部比特，解除了桥电容器只有基本尺寸电容器（1C），可以精确地实现，并改善了精度eseoui较低位而无需额外补偿电路。
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公开(公告)号：KR1020150041515A
公开(公告)日：2015-04-16
申请号：KR1020130120134
申请日：2013-10-08
Applicant: 주식회사 실리콘웍스
Inventor： 김현식
CPC classification number: H03M1/0621 , G09G3/36 , H03M1/16 , H03M1/66 , H03M2201/194 , H03M2201/8152
Abstract: 전압보간회로는복수의전원터미널들; 복수의커패시터들; 및제어신호에따라상기커패시터들및 상기복수의전원터미널들의직렬연결과상기커패시터들의병렬연결을교번적으로수행하는스위칭부를포함한다. 따라서, 전압보간회로및 디지털-아날로그변화회로는복수의커패시터를반복적으로직렬및 병렬연결하여보간회로내 소자간소자간부정합(mismatching)과기생소자와무관하게균일한전압을생성할수 있다.
Abstract translation: 提供电压内插电路和数模转换器（DAC）。电压内插电路包括多个电源端子; 多个电容器; 以及开关单元，根据控制信号，串联并联并联电容器和电源端子。 因此，不管元件之间的不匹配和电压内插电路内的寄生元件如何，内插电路和DAC可以通过串联并联地重复连接电容器来产生均匀的电压。
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公开(公告)号：KR101299215B1
公开(公告)日：2013-08-22
申请号：KR1020120025236
申请日：2012-03-12
Applicant: 전자부품연구원
IPC: H03M1/38
CPC classification number: H03M1/38 , H03M1/1023 , H03M2201/2233 , H03M2201/63 , H03M2201/8152
Abstract: PURPOSE: A method for correcting a capacitor mismatch and an analog-to-digital converter (ADC) using thereof are provided to correct a mismatch between capacitors regardless of the bit numbers of a lower bit and an upper bit. CONSTITUTION: An ADC comprises a capacitor array unit (100) and a correction unit (400). The capacitor array unit includes a separable weighting capacitor having a first end connected to a left unit capacitor row and a second end connected to a right capacitor row; and a correction capacitor connected directly between the first end and a ground terminal the separable weighting capacitor. The capacitor array unit collects a sample of differences between a first reference voltage and an analog input voltage using the right unit capacitor row and the left unit capacitor row in a capacitor mismatch mode. The correction unit determines whether a capacitor mismatch occurs or not based on a digital signal, and changes capacitance of the correction capacitor if the capacitor mismatch occurs.
Abstract translation: 目的：提供一种用于校正电容器失配的方法和使用其的模数转换器（ADC），以校正电容器之间的失配，而与低位和高位的位数无关。 构成：ADC包括电容器阵列单元（100）和校正单元（400）。 电容器阵列单元包括可分离加权电容器，其具有连接到左单元电容器行的第一端和连接到右电容器行的第二端; 以及直接连接在第一端和接地端子之间的可分离加权电容器的校正电容器。 电容器阵列单元使用正确的单位电容器行和左单位电容器行以电容器失配模式收集第一参考电压和模拟输入电压之间的差异样本。 校正单元基于数字信号确定是否发生电容器失配，并且如果发生电容器失配则改变校正电容器的电容。
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公开(公告)号：KR1020130052916A
公开(公告)日：2013-05-23
申请号：KR1020110118255
申请日：2011-11-14
Applicant: 주식회사 실리콘웍스
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M2201/61 , H03M2201/62 , H03M2201/8152 , H03M2201/932
Abstract: PURPOSE: A digital analog converter which applies an electric charge subtraction method is provided to minimize errors of capacitors and relatively reduce a size of a decoder. CONSTITUTION: A control signal generating device(340) generates a switch control signal in response to digital data of N bits. A resistance string(310) comprises a first resistor array, a second resistor array, and a third resistor array which respectively divide multiple resistances which are connected between a reference voltage and a grounding voltage in series. A switch block(320) outputs a selection voltage by switching a part of voltage which is applied to any node of multiple serial resistances respectively included in the first resistor array, the second resistor array, and the third resistor array in response to the switch control signal. A conversion voltage generating block(330) generates a conversion voltage in response to a negative phase clock signal which is opposite to a positive phase clock signal.
Abstract translation: 目的：提供一种应用电荷减法的数字模拟转换器，以最小化电容器的误差并相对减小解码器的尺寸。 构成：响应于N位的数字数据，控制信号产生装置（340）产生开关控制信号。 电阻串（310）包括分别分别连接在参考电压和接地电压之间的多个电阻的第一电阻器阵列，第二电阻器阵列和第三电阻器阵列。 开关块（320）响应于开关控制切换施加到分别包括在第一电阻器阵列，第二电阻器阵列和第三电阻器阵列中的多个串联电阻的任何节点的电压的一部分来输出选择电压 信号。 转换电压产生块（330）响应于与正相位时钟信号相反的负相位时钟信号产生转换电压。
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Patent Agency Ranking16.发明公开Switched-capacitor cyclic digital to analog converter with capacitor mismatch compensation 有权开关电容循环数字到具有电容器误差补偿的模拟转换器
公开(公告)号：KR20120021021A
公开(公告)日：2012-03-08
申请号：KR20100085037
申请日：2010-08-31
Applicant: UNIV SOGANG IND UNIV COOP FOUN
Inventor： LEE YONG MIN , LEE KYE SHIN
IPC: H03M1/66
CPC classification number: H03M1/1023 , H03M1/66 , H03M2201/62 , H03M2201/63 , H03M2201/8152
Abstract: PURPOSE: A digital to analog converter for revising mismatch between capacitors is provided to reduce error possibility in a display output by revising errors due to mismatch between capacitors. CONSTITUTION: A DAC(Digital To Analog Converter) is composed of three capacitors(C1,C2,C3) with the same capacity as one operational amplifier(10) and switches(S1-S9). The operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The second input terminal is connected to a ground terminal. A second capacitor and a third capacitor are used to revise mismatch between capacitors. The first capacitor, the second capacitor, the third capacitor, and the operational amplifier are differently connected for sampling and mismatch correction according to a turn on and off operation of the switch.
Abstract translation: 目的：提供用于修改电容器之间不匹配的数模转换器，通过修改由于电容器之间的不匹配造成的误差，可以减少显示输出中的错误可能性。 构成：DAC（数模转换器）由三个电容（C1，C2，C3）组成，与一个运算放大器（10）和开关（S1-S9）的容量相同。 运算放大器包括第一输入端，第二输入端和输出端。 第二输入端子连接到接地端子。 使用第二电容器和第三电容器来修正电容器之间的失配。 根据开关的接通和断开操作，第一电容器，第二电容器，第三电容器和运算放大器被不同地连接用于采样和不匹配校正。
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公开(公告)号：KR101878593B1
公开(公告)日：2018-07-13
申请号：KR1020170021362
申请日：2017-02-17
Applicant: 서울대학교산학협력단
CPC classification number: H03M1/06 , H03M1/186 , H03M2201/6128 , H03M2201/8152
Abstract: 본기술에의한아날로그디지털변환기는입력전압을기준전압과비교하는제 1 비교기; 제 1 노드의전압을공통전압과비교하는제 2 비교기; 제 1 노드에일단이연결된다수의커패시터를포함하는커패시터어레이; 다수의커패시터의타단을제어하는다수의스위치를포함하는스위치어레이; 제 1 비교기와제 2 비교기의출력에따라스위치어레이를제어하는제어부; 및샘플링신호에따라입력전압을제 1 노드에제공하는샘플링스위치를포함한다.
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公开(公告)号：KR101834975B1
公开(公告)日：2018-04-20
申请号：KR1020170029311
申请日：2017-03-08
Applicant: 충북대학교 산학협력단
CPC classification number: H03M1/38 , H03M1/1245 , H03M2201/62 , H03M2201/8152
Abstract: 본발명은분리형단조연속근사아날로그디지털변환기에관한것으로서, 연속근사레지스터(SAR) 제어로직에의해스위칭제어에대응하여입력신호인제1입력신호(V)와제2입력신호(V)를입력받아샘플동작및 홀드동작을수행하는샘플홀드부와, 샘플홀드시간동안제1입력신호와제2입력신호에대해각각에대응되는출력전압값인제1출력신호와제2출력신호로생성하며, 브릿지커패시터(C)를상위비트또는하위비트를결정하기위한커패시터어레이를 2단구조로형성한커패시터어레이와, 샘플홀드부와연동되어상위비트또는하위비트를결정하는스위치(S7)와, 제1출력신호와제2출력신호의크기를비교하여비교결과에따라디지털값을출력하는비교기와, 디지털값에대응하여최종디지털코드값을결과신호로출력하는연속근사레지스터제어로직을포함한다. 본발명에따르면, 분리형과단조를조합하여커패시터개수감소, 에너지효율향상, 커패시터크기구현가능, 정확도향상등의효과를기대할수 있다.
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公开(公告)号：KR1020130110557A
公开(公告)日：2013-10-10
申请号：KR1020120032598
申请日：2012-03-29
Applicant: 주식회사 팝코아테크 , 김남걸
Inventor： 김남걸
CPC classification number: H03M1/66 , H03M3/30 , H03M2201/61 , H03M2201/8152
Abstract: PURPOSE: A digital-analog converter for a multi-bit sigma-delta modulator is provided to enable the multi-bit sigma-delta modulator to process an output signal including a lot of bits and include resolution. CONSTITUTION: A digital-analog converter for a multi-bit sigma-delta modulator includes a positive polarity unit (110), a negative polarity unit (120), and a differential amplifier (130). The positive polarity unit outputs a positive polarity reference voltage according to the output signal of a digital filter. The negative polarity unit outputs a negative polarity reference voltage according to the output signal. The differential amplifier receives the positive polarity reference voltage and the negative polarity reference voltage and outputs a positive polarity voltage and a negative polarity voltage.
Abstract translation: 目的：提供用于多位Σ-Δ调制器的数模转换器，以使多位Σ-Δ调制器能够处理包括大量位的输出信号并包括分辨率。 构成：用于多位Σ-Δ调制器的数模转换器包括正极性单元（110），负极性单元（120）和差分放大器（130）。 正极性单元根据数字滤波器的输出信号输出正极参考电压。 负极性单元根据输出信号输出负极性参考电压。 差分放大器接收正极参考电压和负极性参考电压，并输出正极性电压和负极性电压。
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20.发明公开
公开(公告)号：KR1020110106568A
公开(公告)日：2011-09-29
申请号：KR1020100025672
申请日：2010-03-23
Applicant: 고려대학교 산학협력단
IPC: H03M1/66
CPC classification number: H03M1/14 , H03M1/002 , H03M1/48 , H03M2201/62 , H03M2201/8152 , H03M2201/932
Abstract: 본 발명은 캐패시터의 직렬연결을 이용하여 멀티플라잉 디지털 아날로그 변환기의 구성에 사용되는 캐패시터의 숫자를 줄여 칩 면적과 소모 전력을 줄인 멀티플라잉 디지털 아날로그 변환기 및 이를 이용한 파이프라인 아날로그 디지털 변환기에 관한 것으로, 본 발명에 따른 멀티플라잉 디지털 아날로그 변환기는 샘플링페이즈에서 입력전압을 입력받고 증폭페이즈에서 상기 샘플링페이즈에서 보다 캐패시턴스 값이 줄어드는 제1캐패시터부; 상기 샘플링페이즈에서 상기 입력전압을 입력받고 상기 증폭페이즈에서 디지털 전압을 입력받는 제2캐패시터부; 및 상기 샘플링페이즈에서 상기 제1캐패시터부와 상기 제2캐패시터부가 입력받은 입력전압과 상기 증폭페이즈에서 상기 제2캐패시터부가 입력받은 디지털전압의 차이를 증폭한 레지듀 전압을 출력하기 위한 증폭부를 포함하고, 상기 제1캐패시터부는 상기 증폭페이즈에서 상기 증폭부의 입력노드와 출력노드사이에 네거티브 피드백 루프를 이루는 것을 특징으로 한다.
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