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    DIFFERENTIAL INTERCONNECT TOPOLOGY IN A SUBSTRATE WITH STAGGERED VIAS
    243.
    发明申请
    DIFFERENTIAL INTERCONNECT TOPOLOGY IN A SUBSTRATE WITH STAGGERED VIAS 有权
    具有分离VIAS的基底中的差异互连拓扑

    公开(公告)号：US20160172734A1

    公开(公告)日：2016-06-16

    申请号：US14570791

    申请日：2014-12-15

    Applicant: Intel Corporation

    Inventor： Min Wang ,  Russell N. Shryock

    IPC: H01P3/08

    CPC classification number: H05K1/0245 ,  H01P3/026 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09636

    Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.

    Abstract translation: 公开了一种互连拓扑，其包括多个互连，每个互连使用通孔耦合在一起，其中至少两个通孔相对于彼此交错。 在一个实施例中，互连拓扑包括衬底，通过多层上的衬底布线的多个信号迹线以及多个通孔，其中每个通孔耦合一对信号迹线以形成多个不同层之间的互连， 并且其中一对通孔包括第一通孔以承载正差分信号通路和第二通孔，以携带耦合到信号迹线的负差分信号以形成差分信号对。 差分第一和第二通孔相对于彼此交错。

    PRINTED WIRING BOARD
    244.
    发明申请
    PRINTED WIRING BOARD 有权
    印刷线路板

    公开(公告)号：US20160050754A1

    公开(公告)日：2016-02-18

    申请号：US14823519

    申请日：2015-08-11

    Applicant: FANUC Corporation

    Inventor： Makoto BEKKE

    IPC: H05K1/11

    CPC classification number: H05K1/115 ,  H05K3/3447 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2203/044

    Abstract: A printed wiring board includes three or more than three through holes. An inner wall of the through hole is covered by conductive coating. Same size leads of an electronic component are inserted into the through holes. The through holes are soldered by dip soldering the printed wiring board in melting solder. The through holes have two or more diameters. The diameter of the through hole having more adjacent through holes is not larger than the diameter of the through hole having less adjacent through holes.

    Abstract translation: 印刷电路板包括三个或三个以上的通孔。 通孔的内壁被导电涂层覆盖。 将电子部件的相同尺寸的引线插入到通孔中。 通孔通过浸焊焊接印刷线路板而熔化焊料来焊接通孔。 通孔具有两个或更多个直径。 具有更多相邻通孔的通孔的直径不大于具有较少相邻通孔的通孔的直径。

    SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF
    245.
    发明申请
    SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    基板结构及其制造方法

    公开(公告)号：US20150114698A1

    公开(公告)日：2015-04-30

    申请号：US14105195

    申请日：2013-12-13

    Applicant: Tzu-Wei Huang ,  Chin-Sheng Wang

    Inventor： Tzu-Wei Huang ,  Chin-Sheng Wang

    IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K1/09

    CPC classification number: H05K1/115 ,  H05K3/0094 ,  H05K3/421 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09636 ,  H05K2201/09854 ,  Y10T29/302

    Abstract: A substrate structure includes a substrate and a filling material. The substrate has an upper surface, a lower surface, at least one first blind via and at least one second blind via. The substrate includes an insulation layer, a first copper foil layer and a second copper foil layer. The first copper foil layer and the second copper foil layer are respectively disposed on two opposite side surfaces of the insulation layer. The first blind via extends from the upper surface toward the second copper foil layer and exposes a portion of the second copper foil layer. The second blind via extends from the lower surface toward the first copper foil layer and exposes a portion of the first copper foil layer. The filling material is filled inside of the first blind via and the second blind via and covers the upper surface and the lower surface of the substrate.

    Abstract translation: 衬底结构包括衬底和填充材料。 衬底具有上表面，下表面，至少一个第一盲孔和至少一个第二盲孔。 基板包括绝缘层，第一铜箔层和第二铜箔层。 第一铜箔层和第二铜箔层分别设置在绝缘层的两个相对的侧表面上。 第一盲孔从上表面延伸到第二铜箔层并暴露第二铜箔层的一部分。 第二盲孔从下表面延伸到第一铜箔层并暴露第一铜箔层的一部分。 填充材料填充在第一盲孔和第二盲孔内部并覆盖基板的上表面和下表面。

    MULTI LAYERED PRINTED CIRCUIT BOARD
    246.
    发明申请
    MULTI LAYERED PRINTED CIRCUIT BOARD 审中-公开
    多层印刷电路板

    公开(公告)号：US20150053475A1

    公开(公告)日：2015-02-26

    申请号：US14463489

    申请日：2014-08-19

    Applicant: Samsung Electro-Mechanics Co., Ltd.

    Inventor： Jung Keun Kim

    IPC: H05K1/11 ,  H05K1/02

    CPC classification number: H05K1/0265 ,  H05K1/115 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/09836 ,  H05K2201/09854

    Abstract: There is provided a multi layered printed circuit board. The multi layered printed circuit board according to an exemplary embodiment of the present disclosure includes: a plurality of circuit layers; insulating layers each formed between the plurality of circuit layers; and a via penetrating through the insulating layers and the circuit layers and electrically connecting the plurality of circuit layers to each other, wherein the via includes a first via and a second via, and the second via is a large diameter via having a diameter larger than that of the first via.

    Abstract translation: 提供了多层印刷电路板。 根据本公开的示例性实施例的多层印刷电路板包括：多个电路层; 绝缘层各自形成在所述多个电路层之间; 以及穿过绝缘层和电路层并且将多个电路层彼此电连接的通孔，其中所述通孔包括第一通孔和第二通孔，并且所述第二通孔是大直径通孔，其直径大于 那第一个通过。

    Multilayer substrate
    247.
    发明授权
    Multilayer substrate 有权
    多层基板

    公开(公告)号：US08536464B2

    公开(公告)日：2013-09-17

    申请号：US12994774

    申请日：2008-05-26

    Applicant: Taras Kushta ,  Jun Sakai ,  Hikaru Kouta

    Inventor： Taras Kushta ,  Jun Sakai ,  Hikaru Kouta

    IPC: H05K1/11

    CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

    Abstract: A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.

    Abstract translation: 多层基板设置有布置有多个导体平面的导体平面区域; 与所述导体平面区域相邻设置的间隙区域，以使所述多个导体平面从所述间隙区域排除。 多个信号通孔设置穿过间隙区域，使得多个信号通孔与多个导体平面隔离。 导体柱连接到多个导体平面中的一个并且设置在间隙区域中的两个信号通孔之间。

    Multi-layer substrate
    248.
    发明授权
    Multi-layer substrate 有权
    多层基板

    公开(公告)号：US08476537B2

    公开(公告)日：2013-07-02

    申请号：US12675678

    申请日：2007-08-31

    Applicant: Taras Kushta

    Inventor： Taras Kushta

    IPC: H05K1/11

    CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09781

    Abstract: A multi-layer substrate includes a planar transmission line structure and a signal via, which are connected by a multi-tier transition. The multi-tier transition includes a signal via pad configured to serve for a full-value connection of the signal via and the planar transmission line; and a dummy pad connected to the signal via, formed in an area of a clearance hole in a conductor layer disposed between a signal terminal of the signal via and the planar transmission line, and isolated from the conductor layer.

    Abstract translation: 多层基板包括通过多层转换连接的平面传输线结构和信号通孔。 多层转换包括经配置以用于信号通孔和平面传输线的全值连接的信号通孔; 以及连接到信号通孔的虚拟焊盘，形成在布置在信号通孔的信号端子和平面传输线之间并与导体层隔离的导体层中的间隙孔的区域中。

    Multilayer printed circuit board
    249.
    发明授权
    Multilayer printed circuit board 有权
    多层印刷电路板

    公开(公告)号：US08304667B2

    公开(公告)日：2012-11-06

    申请号：US12920426

    申请日：2009-03-24

    Applicant: Takashi Yoshinaga ,  Kenji Kataoka ,  Michihito Otsuki

    Inventor： Takashi Yoshinaga ,  Kenji Kataoka ,  Michihito Otsuki

    IPC: H05K1/11

    CPC classification number: H05K1/0216 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10545 ,  H05K2201/10689

    Abstract: A multilayer printed circuit board, including: a signal interconnection which transmits and receives an electrical signal between electronic components; a ground interconnection connected to a ground of a circuit; a power interconnection connected to a power layer to supply power to electronic components; at least one ground layer installed in an inner layer; at least one clearance which passes through the ground layer; and a ground via which connects the ground interconnection with the ground layer. The signal interconnection and the ground interconnection or the signal interconnection and the power interconnection are installed in a pair, and a pair of interconnection vias for interlayer connection are inserted through the clearance installed in the ground layer so that one of the pair of interconnection vias is connected to the ground layer by the ground interconnection.

    Abstract translation: 一种多层印刷电路板，包括：在电子部件之间传输和接收电信号的信号互连; 连接到电路的地的接地互连; 连接到功率层以向电子部件供电的电力互连; 至少一个地层安装在内层中; 至少一个通过地层的间隙; 以及将接地互连与接地层连接的接地。 信号互连和接地互连，信号互连和电源互连成对安装，并且用于层间连接的一对互连通孔穿过安装在接地层中的间隙插入，使得一对互连通孔中的一个 通过地面互连连接到地层。

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