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    SEMICONDUCTOR POWER DEVICE WITH MULTIPLE DRAIN AND CORRESPONDING MANUFACTURING PROCESS
    251.
    发明授权
    SEMICONDUCTOR POWER DEVICE WITH MULTIPLE DRAIN AND CORRESPONDING MANUFACTURING PROCESS 有权
    具有多个排出及相关制造工艺半导体功率器件

    公开(公告)号：EP1908101B1

    公开(公告)日：2012-12-26

    申请号：EP06762481.7

    申请日：2006-07-07

    Applicant: STMicroelectronics Srl

    Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

    CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

    Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity, comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity and of a first resistivity (Á 1 ) value on the semiconductor substrate (100), forming at least a second semiconductor layer (22) of a second type of conductivity of a second resistivity (Á 2 ) value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity by means of a first selective implant step with a first implant dose (¦ 1 ) , forming, above this at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity of a third resistivity (Á 6 ) value, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of the semiconductor layer (22) free from the plurality of implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D) along this at least a second semiconductor layer (22), the plurality of column implanted regions (D) delimiting a plurality of column regions (50) of the second type of conductivity aligned with the body regions (40).

    Method and circuit for cryptographic operation
    254.
    发明公开
    Method and circuit for cryptographic operation 有权
    Verfahren und Schaltungfürkryptografische操作

    公开(公告)号：EP2523385A1

    公开(公告)日：2012-11-14

    申请号：EP11164951.3

    申请日：2011-05-05

    Applicant: PROTON WORLD INTERNATIONAL N.V. ,  STMicroelectronics Srl

    Inventor： Van Assche, Gilles ,  Daemen, Joan ,  Bertoni, Guido Marco

    IPC: H04L9/06

    CPC classification number: H04L9/002 ,  H04L9/004 ,  H04L9/06 ,  H04L2209/12

    Abstract: The invention concerns a method of performing a cryptographic operation comprising: receiving a plurality of binary input values (P 0 ...P N ); splitting said binary input values into a plurality of non-binary digits (P 0 '...P M ') of base r, where r is an integer greater than 2 and not equal to a power of 2; and performing, by a cryptographic block (306) on each of the plurality of non-binary digits, a different modulo r operation to generate at least one output digit (Z 0 '...Z M ') of base r.

    Abstract translation: 本发明涉及一种执行密码操作的方法，包括：接收多个二进制输入值（P 0 ... P N）; 将所述二进制输入值分解为基本r的多个非二进制数字（P 0'... P M'），其中r是大于2且不等于2的幂的整数; 并且通过在所述多个非二进制数字中的每一个上的密码块（306）执行不同的模r操作以生成基本r的至少一个输出数字（Z 0'... Z M'）。

    Process for manufacturing a membrane microelectromechanical device and membrane microelectromechanical device
    258.
    发明公开
    Process for manufacturing a membrane microelectromechanical device and membrane microelectromechanical device 有权
    Verfahren zur Herstellung einer mikroelektromechanischen Membranvorrichtung und mikroelektromechanische Membranvorrichtung

    公开(公告)号：EP2500313A1

    公开(公告)日：2012-09-19

    申请号：EP12160022.5

    申请日：2012-03-17

    Applicant: STMicroelectronics Srl

    Inventor： Corona, Pietro ,  Ferrera, Marco ,  Varisco, Igor ,  Campedelli, Roberto

    IPC: B81C1/00 ,  G01L9/00

    CPC classification number: B81C1/00158 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C1/00293 ,  B81C2203/0145 ,  G01L9/0042 ,  G01L9/0073

    Abstract: A process for manufacturing a microelectromechanical device envisages: forming a semiconductor structural layer (3) separated from a substrate (2) by a dielectric layer (4), and opening trenches (10) through the structural layer (3), as far as the dielectric layer (4). Sacrificial portion (4a) of the dielectric layer (4) are selectively removed through the trenches (10) in membrane regions (M) so as to free a corresponding portion of the structural layer (3) that forms a membrane (11). To close the trenches (10), the wafer (1) is brought to an annealing temperature for a time interval in such a way as to cause migration of the atoms of the membrane (11) so as to reach a minimum energy configuration.

    Abstract translation: 微机电装置的制造方法设想：通过介电层（4）形成与基板（2）分离的半导体结构层（3），通过结构层（3）形成开口沟槽（10），只要 电介质层（4）。 电介质层（4）的牺牲部分（4a）通过膜区域（M）中的沟槽（10）被选择性地去除，以便释放形成膜（11）的结构层（3）的相应部分。 为了封闭沟槽（10），使得晶片（1）以使得膜（11）的原子迁移以达到最小能量构型的方式达到退火温度一段时间间隔。

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