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公开(公告)号：KR1020150134857A
公开(公告)日：2015-12-02
申请号：KR1020140062213
申请日：2014-05-23
Applicant: 삼성전기주식회사
CPC classification number: H01F17/0013 , H01F27/2804 , H01F27/292 , H01F41/041 , H01F2027/2809
Abstract: 본발명은절연기판과상기절연기판의내부에임베딩된코일도체패턴을포함하는자성체본체; 및상기코일도체패턴의단부와연결되도록상기자성체본체의양 단부에형성된외부전극;을포함하며, 상기코일도체패턴은내부에복수개의에칭면이형성된칩 전자부품에관한것이다.
Abstract translation: 芯片电子部件技术领域本发明涉及芯片电子部件，其特征在于，包括：绝缘基板的绝缘基板和嵌入在所述绝缘基板内的线圈导电图案的磁性体的主体; 以及形成在磁性材料的主体的两个端部中的外部电极，以连接到线圈导电图案的端部。 线圈导电图案具有内部形成的多个蚀刻面。
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22.发明公开박막 인덕터용 코일 유닛, 박막 인덕터용 코일 유닛의 제조방법, 박막 인덕터 및 박막 인덕터의 제조방법 审中-实审薄膜电感线圈单元，薄膜电感线圈单元的制造方法，薄膜电感器及薄膜电感器的制造方法
公开(公告)号：KR1020150019588A
公开(公告)日：2015-02-25
申请号：KR1020130096649
申请日：2013-08-14
Applicant: 삼성전기주식회사
CPC classification number: H01F41/041 , H01F17/0013 , H01F41/046 , H01F2017/0066 , Y10T29/49071
Abstract: 본 발명은 박막 인덕터용 코일 유닛, 박막 인덕터용 코일 유닛의 제조방법, 박막 인덕터 및 박막 인덕터의 제조방법에 관한 것이다.
본 발명에 따른 박막 인덕터용 코일 유닛은, 서로 다른 재질의 이중의 절연층을 갖는 절연재; 상기 절연재의 상하면에 각각 내장 형성되는 코일패턴;을 포함하되, 상기 코일패턴은, 복수의 도금층으로 형성된 코일패턴을 포함한다.
또한 본 발명에 따른 박막 인덕터용 코일 유닛의 제조방법은, 접착층을 매개로 기재층의 양면에 각각 접착되는 한 쌍의 금속층 각각에 제1 코일패턴을 형성하는 단계; 상기 제1 코일패턴을 내장하도록 제1 절연층을 형성하는 단계; 복수의 도금층으로 형성된 제2 코일패턴을 내장하도록, 상기 제2 코일패턴 및 제2 절연층을 형성하는 단계; 상기 기재층으로부터 한 쌍의 금속층을 분리하는 단계;를 포함하되, 상기 제1 절연층 및 상기 제 2 절연층은 서로 다른 재질로 형성된다.Abstract translation: 本发明涉及一种用于薄膜电感器的线圈单元，其制造方法，薄膜电感器及其制造方法。 根据本发明，薄膜电感线圈单元包括：具有不同材料双重绝缘层的绝缘材料; 以及形成为安装在所述绝缘层的上侧和下侧内部的线圈图案，其中所述线圈图案形成在多个镀层上。 此外，根据本发明的薄膜电感器线圈单元的制造方法包括以下步骤：在一对金属层中的每一个上形成第一线圈图案，该金属层通过粘合剂粘附到基层的两侧中的每一侧 层; 形成要安装在第一线圈图案内的第一绝缘层; 形成第二线圈图案和第二绝缘层，以安装在第二线圈图案内部以形成在多个镀层上; 以及从所述基底层分离一对金属层，其中所述第一和第二绝缘层分别形成为不同的材料。
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公开(公告)号：KR1020100061026A
公开(公告)日：2010-06-07
申请号：KR1020080119895
申请日：2008-11-28
Applicant: 삼성전기주식회사
IPC: H05K3/40
CPC classification number: H05K1/111 , H05K1/09 , H05K1/115 , H05K3/205 , H05K3/28 , H05K3/4007 , H05K2201/0367 , H05K2203/0323 , H05K2203/0376 , Y02P70/611 , Y10T29/49124 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
Abstract: PURPOSE: A printed circuit board including a metal bump and a manufacturing method thereof are provided to improve transmission performance of an electric signal by including the metal bump without a bump pad. CONSTITUTION: A groove part for forming a metal bump is formed on a metal carrier. A barrier layer is formed on the metal carrier and includes the groove part. An upper circuit layer including a metal bump(615) and a circuit pattern(610) is formed on the barrier layer. A circuit layer is transferred on an insulation layer(400). The metal carrier and the barrier layer are removed. A solder resist layer(700) is formed on the insulation layer.
Abstract translation: 目的：提供一种包括金属凸块的印刷电路板及其制造方法，以通过包括没有凸块焊盘的金属凸块来提高电信号的传输性能。 构成：在金属载体上形成用于形成金属凸块的槽部。 在金属载体上形成阻挡层，并且包括槽部。 在阻挡层上形成包括金属凸块（615）和电路图案（610）的上电路层。 电路层转移到绝缘层（400）上。 去除金属载体和阻挡层。 在绝缘层上形成阻焊层（700）。
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公开(公告)号：KR1020100010253A
公开(公告)日：2010-02-01
申请号：KR1020080071153
申请日：2008-07-22
Applicant: 삼성전기주식회사
CPC classification number: B32B38/04 , B32B38/10 , B32B2038/0092 , B32B2038/047 , B32B2309/105 , B32B2310/0843 , B32B2457/08 , H05K3/0035 , H05K3/108 , H05K3/421 , H05K3/428 , H05K3/4652 , H05K2201/0376 , H05K2203/0384 , H05K2203/0554 , Y10T156/1056 , Y10T156/1057 , Y10T156/1064 , Y10T156/1082
Abstract: PURPOSE: A method for manufacturing a printed circuit board is provided to easily secure a shape of a via hole by reducing an amount of energy for forming the via hole. CONSTITUTION: A barrier layer is formed on one side of a carrier(S112). A circuit pattern is formed on the barrier layer(S116). A groove corresponding to the via is formed on one side of the carrier(S120). One side of the carrier is compressed to one side of an insulator(S130). The carrier is removed(S140). A via hole corresponding to the groove is formed on the insulator(S150). A conductive material is formed inside the via hole(S160).
Abstract translation: 目的：提供一种制造印刷电路板的方法，通过减少用于形成通孔的能量来容易地确保通孔的形状。 构成：在载体的一侧形成阻挡层（S112）。 在阻挡层上形成电路图案（S116）。 在载体的一侧形成与通孔相对应的槽（S120）。 载体的一侧被压缩到绝缘体的一侧（S130）。 移除载体（S140）。 在绝缘体上形成与沟槽对应的通路孔（S150）。 导电材料形成在通孔内（S160）。
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公开(公告)号：KR1020090002718A
公开(公告)日：2009-01-09
申请号：KR1020070066894
申请日：2007-07-04
Applicant: 삼성전기주식회사
IPC: H05K3/00
CPC classification number: H05K3/205 , H05K3/108 , H05K3/4602 , H05K2203/1536 , Y10T428/249984 , Y10T428/31504 , Y10T428/31511 , Y10T428/3154 , Y10T428/31678 , Y10T428/31721 , Y10T428/31993
Abstract: The carrier and manufacturing method of PCB are provided to shorten the manufacturing process by forming the circuit pattern on a pair of releasing layer through one process. The carrier(10) comprises the base material layer(12), and a pair of the bonding layer(14) and pair of the releasing layer(16). A pair of bonding layer is laminated on both sides of the base material layer. The adhesive force of a pair of bonding layer is degraded by the predetermined factor. A pair of releasing layer is adhered at each bonding layer. The releasing layer comprises one of the conductive metal or the insulating material.
Abstract translation: 提供PCB的载体和制造方法，以通过一个工艺在一对释放层上形成电路图案来缩短制造过程。 载体（10）包括基材层（12）和一对粘合层（14）和一对释放层（16）。 在基材层的两侧层叠一对接合层。 一对结合层的粘合力降低预定因子。 在每个接合层处粘附一对释放层。 释放层包括导电金属或绝缘材料之一。
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Patent Agency Ranking
公开(公告)号：KR1020080037307A
公开(公告)日：2008-04-30
申请号：KR1020060104203
申请日：2006-10-25
Applicant: 삼성전기주식회사
IPC: H05K3/20
CPC classification number: H05K1/0265 , H05K1/116 , H05K3/107 , H05K3/108 , H05K3/205 , H05K3/421 , H05K2201/0379 , H05K2201/0394 , H05K2201/09509 , H05K2201/09736 , H05K2203/0361
Abstract: A circuit board and a method for manufacturing the same are provided to reduce a thickness of the entire circuit board and a material cost by forming the multi-layered circuit board without addition of an insulator. A method for manufacturing a circuit board includes the steps of: forming a conductive relief pattern with a sequentially stacked first plating layer, a first metal layer, and a second plating layer on a seed layer of a carrier with the stacked seed layers to correspond to a first circuit pattern(S100); stacking an insulator and one surface of the carrier with the conductive relief pattern to face each other and compressing the stacked insulator and carrier(S200); transferring the conductive relief pattern to the insulator by removing the carrier(S300); forming a conductive pattern with the sequentially stacked third plating layer and the second metal layer on one surface of the insulator with the transferred conductive relief pattern to correspond to a second circuit pattern(S400); removing the first plating layer and the seed layer(S500); and removing the first metal layer and the second metal layer(S600).
Abstract translation: 提供一种电路板及其制造方法，以通过在不添加绝缘体的情况下形成多层电路板来减小整个电路板的厚度和材料成本。 一种电路板的制造方法，其特征在于，具有：在层叠种子层的载体的种子层上形成具有顺序层叠的第一镀层，第一金属层和第二镀层的导电性浮雕图案，以对应于 第一电路图案（S100）; 用导电凸版图案堆叠绝缘体和载体的一个表面以彼此面对并压缩堆叠的绝缘体和载体（S200）; 通过移除载体将导电浮雕图案转印到绝缘体上（S300）; 在所述绝缘体的一个表面上依次堆叠的第三镀层和所述第二金属层与所述转移的导电浮雕图案形成导电图案以对应于第二电路图案（S400）; 去除第一镀层和种子层（S500）; 并移除第一金属层和第二金属层（S600）。
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公开(公告)号：KR100782402B1
公开(公告)日：2007-12-07
申请号：KR1020060103455
申请日：2006-10-24
Applicant: 삼성전기주식회사
IPC: H05K3/20
CPC classification number: H05K3/205 , H05K1/11 , H05K3/3457 , H05K3/4007 , H05K2201/0394
Abstract: A printed circuit board and its manufacturing method are provided to implement a fine pattern by forming a circuit with a seed layer through an additive method. A method for manufacturing a printed circuit board includes the steps of: forming a first circuit pattern and a first pump protruded from the first circuit pattern on a carrier plate(S10); burying the first circuit pattern and the first bump on one side of an insulation substrate by pressing the carrier plate on the insulation substrate(S20); and forming a second circuit pattern electrically connected to the first bump on the other side of the insulation substrate(S30).
Abstract translation: 提供一种印刷电路板及其制造方法，以通过添加方法形成具有种子层的电路来实现精细图案。 一种制造印刷电路板的方法包括以下步骤：在载板上形成从第一电路图形突出的第一电路图案和第一泵; 通过将绝缘基板上的承载板压在绝缘基板的一侧上来掩埋第一电路图案和第一凸块（S20）; 以及形成与所述绝缘基板的另一侧上的所述第一凸块电连接的第二电路图案（S30）。
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公开(公告)号：KR100782407B1
公开(公告)日：2007-12-05
申请号：KR1020060105924
申请日：2006-10-30
Applicant: 삼성전기주식회사
IPC: H05K3/20
CPC classification number: H05K3/20 , H05K3/0058 , H05K3/108 , H05K3/4611 , H05K3/4682 , H05K2201/0394 , H05K2201/09481 , H05K2201/09518 , H05K2201/09563 , H05K2203/0152 , H05K2203/0376 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
Abstract: A method for manufacturing a circuit board is provided to reduce the whole thickness of a substrate by embedding a circuit pattern on the substrate and transferring a thin insulation layer on the substrate. A method for manufacturing a circuit board includes the steps of: forming a first circuit pattern on an insulation layer of a carrier on which the insulation layer and a first seed layer are sequentially stacked(S100); stacking one side of the carrier having the first circuit pattern to face an insulation substrate and compressing the carrier and the insulation substrate(S200); removing the carrier to transfer the first circuit pattern and the insulation layer on the insulation substrate(S300); and forming a second circuit pattern on the insulation layer transferred on the insulation substrate(S400).
Abstract translation: 提供一种制造电路板的方法，通过将电路图案嵌入衬底并在衬底上传输薄绝缘层来减小衬底的整体厚度。 一种制造电路板的方法包括以下步骤：在绝缘层和第一种子层依次层叠的载体的绝缘层上形成第一电路图案（S100）; 堆叠具有第一电路图案的载体的一侧面对绝缘基板并压缩载体和绝缘基板（S200）; 移除载体以将第一电路图案和绝缘层转移到绝缘基板上（S300）; 以及在绝缘层上转移的绝缘层上形成第二电路图案（S400）。
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公开(公告)号：KR100771467B1
公开(公告)日：2007-10-30
申请号：KR1020060105923
申请日：2006-10-30
Applicant: 삼성전기주식회사
IPC: H05K1/02
CPC classification number: H05K3/205 , H01L21/4846 , H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/15311 , H05K3/4007 , H05K2201/09745 , H05K2201/10674 , H05K2203/0338 , H05K2203/0435 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
Abstract: A circuit board and a manufacturing method thereof are provided to reduce the entire thickness of a package by condensing a solder in a substrate and to adjust an amount of a solder. A circuit board includes an insulation material(16), a circuit layer(24), a solder pad(20), and a circuit pattern(26). The insulation material includes a groove thereon. The circuit layer fills a portion of the grooves. The solder pad is formed on the circuit layer to fill the rest grooves. The circuit pattern is electrically connected to the circuit layer. A portion of the circuit pattern is buried by the insulation material such that the circuit pattern is exposed from a surface of the insulation material. The circuit patterns are buried on both sides of the insulation material. A metal film is applied between the circuit layer and the solder pad.
Abstract translation: 提供一种电路板及其制造方法，通过将衬底中的焊料冷凝并调整焊料的量来减小封装的整体厚度。 电路板包括绝缘材料（16），电路层（24），焊盘（20）和电路图案（26）。 绝缘材料在其上包括凹槽。 电路层填充一部分凹槽。 焊盘形成在电路层上以填充其余的沟槽。 电路图案电连接到电路层。 电路图案的一部分被绝缘材料掩埋，使得电路图案从绝缘材料的表面露出。 电路图案埋在绝缘材料的两侧。 在电路层和焊盘之间施加金属膜。
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公开(公告)号：KR100728758B1
公开(公告)日：2007-06-19
申请号：KR1020060027461
申请日：2006-03-27
Applicant: 삼성전기주식회사
Abstract: A pattern coil printed circuit board and a manufacturing method thereof are provided to increase a rotation force of a motor by acquiring the maximum cross section of a circuit pattern of a pattern coil substrate. A method for manufacturing a pattern coil printed circuit board includes the steps of: forming a first circuit pattern on a surface of a carrier plate(S31); stacking the carrier plate on an insulation layer and burying the first circuit pattern in the insulation layer(S32); removing the carrier plate(S33); and stacking a second circuit pattern which is electrically connected to the first circuit pattern(S34). A seed layer is stacked on the surface of the carrier plate. The S31 step includes the steps of: stacking a plating resist layer on a surface of the seed layer; removing a part of the plating resist layer in correspondence to a forming position of the first circuit pattern; and forming the first circuit pattern by plating the surface of the seed layer.
Abstract translation: 提供图案线圈印刷电路板及其制造方法，以通过获取图案线圈基板的电路图案的最大横截面来增加电动机的旋转力。 一种用于制造图案线圈印刷电路板的方法，包括以下步骤：在承载板的表面上形成第一电路图案（S31）; 将承载板堆叠在绝缘层上并将第一电路图案埋入绝缘层中（S32）; 移除承载板（S33）; 以及堆叠电连接到第一电路图案的第二电路图案（S34）。 种子层堆叠在载体板的表面上。 S31步骤包括以下步骤：在种子层的表面上堆叠抗镀层; 根据第一电路图案的形成位置去除部分抗镀层; 以及通过电镀籽晶层的表面来形成第一电路图案。
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