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公开(公告)号：KR1020130017347A
公开(公告)日：2013-02-20
申请号：KR1020110079726
申请日：2011-08-10
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L21/76897
Abstract: PURPOSE: A semiconductor device is provided to minimize etching damage on a material pattern which stores information and includes a material layer having different etching selectivity. CONSTITUTION: A semiconductor device includes a first molding pattern(3a), a horizontal electrode pattern, a second molding pattern(3b), horizontal patterns and a vertical structured body(19). The vertical structured body includes a vertical electrode pattern, a data storage pattern(13), a first buffer pattern and a second buffer pattern. The vertical structured body passes through the horizontal patterns. The data storage pattern is formed among the vertical electrode pattern and the horizontal patterns.
Abstract translation: 目的：提供半导体器件以最小化存储信息的材料图案上的蚀刻损伤，并且包括具有不同蚀刻选择性的材料层。 构成：半导体器件包括第一成型图案（3a），水平电极图案，第二成型图案（3b），水平图案和垂直结构体（19）。 垂直结构体包括垂直电极图案，数据存储图案（13），第一缓冲图案和第二缓冲图案。 垂直结构体穿过水平图案。 在垂直电极图案和水平图案之间形成数据存储图案。
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公开(公告)号：KR1020120126640A
公开(公告)日：2012-11-21
申请号：KR1020110044612
申请日：2011-05-12
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/04 , H01L27/249 , H01L45/12 , H01L45/1226 , H01L45/146 , H01L27/2409
Abstract: PURPOSE: A non-volatile memory device and a manufacturing method thereof are provided to prevent a filament to be formed in the unwanted place within a resistance alteration film by uniformly forming the filament on the whole curved surface of the resistance alteration film. CONSTITUTION: A plurality of inter layer insulating films are laminated on a substrate by being separated to a second direction(D2). A plurality of first electrodes(115) is extended to the second direction. A plurality of second electrodes(211-291,213-293) is extended to a first direction(D1). A resistance alteration film(116) is placed between the first electrodes and the second electrodes. The resistance alteration film is formed according to the shape of the plurality of first electrodes and the plurality of inter layer insulating films.
Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，以通过在电阻变化膜的整个曲面上均匀地形成丝来防止在电阻变化膜内的不需要的位置形成长丝。 构成：通过分离到第二方向（D2）将多层层间绝缘膜层合在基板上。 多个第一电极（115）延伸到第二方向。 多个第二电极（211-291,213-293）延伸到第一方向（D1）。 电阻变化膜（116）被放置在第一电极和第二电极之间。 电阻改变膜根据多个第一电极和多个层间绝缘膜的形状形成。
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公开(公告)号：KR1020120095571A
公开(公告)日：2012-08-29
申请号：KR1020110014972
申请日：2011-02-21
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L21/28282 , H01L21/28273 , H01L21/76224 , H01L27/11582 , H01L29/7926
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to improve reliability by suppressing residue defects in an interlayer dielectric layer of the uppermost layer. CONSTITUTION: A laminate film pattern(12), a first interlayer dielectric film pattern(14), a first stop film pattern(16), a second interlayer dielectric film pattern(18), and a second stop film pattern(20) are formed on a substrate of a first region. A third interlayer dielectric film pattern is formed on the substrate of a second region. A preliminary channel film pattern which passes through a part of a laminate film, the first interlayer dielectric film pattern, the first stop film pattern, and the second interlayer dielectric film pattern is formed. A part of the preliminary channel film pattern is removed and a residue of a step part on the upper sides of the interlayer dielectric film patterns is removed. A channel pattern structure is formed by polishing the preliminary channel film pattern, the second interlayer dielectric film pattern, and the third interlayer dielectric film pattern.
Abstract translation: 目的：提供一种制造半导体器件的方法，通过抑制最上层的层间电介质层中的残留缺陷来提高可靠性。 构成：形成层叠膜图案（12），第一层间电介质膜图案（14），第一停止膜图案（16），第二层间电介质膜图案（18）和第二停止膜图案（20） 在第一区域的衬底上。 在第二区域的基板上形成第三层间电介质膜图案。 形成通过层压膜的一部分，第一层间电介质膜图案，第一停止膜图案和第二层间电介质膜图案的预备通道膜图案。 除去初步通道膜图案的一部分，去除层间电介质膜图案的上侧的台阶部分的残留物。 通过研磨初步沟道膜图案，第二层间电介质膜图案和第三层间电介质膜图案来形成沟道图案结构。
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公开(公告)号：KR1020120003678A
公开(公告)日：2012-01-11
申请号：KR1020100064411
申请日：2010-07-05
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/788 , H01L23/5384 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L27/0688 , H01L2924/00
Abstract: PURPOSE: A three-dimensional semiconductor device and a manufacturing method thereof are provided to arrange a protection film pattern between a mold film and a plugging pattern, thereby preventing etching damage with respect to the outer surface of the plugging pattern. CONSTITUTION: A first opening part which vertically penetrates a mold film(120) and sacrificial film is arranged. A protection film and a plugging film are successively arranged in an inner wall of the first opening part. A second opening part(200) which is separated from the first opening part while vertically penetrating the mold film and sacrificial film is arranged. A recess region is arranged in order to expose the protection film by eliminating the sacrificial film which is exposed by the second opening part. The plugging film is exposed by eliminating the protection film which is exposed by the recess region.
Abstract translation: 目的：提供三维半导体器件及其制造方法，以在模具膜和封堵图案之间布置保护膜图案，从而防止相对于封堵图案的外表面的蚀刻损伤。 构成：布置垂直穿过模具膜（120）和牺牲膜的第一开口部分。 在第一开口部的内壁依次配置有保护膜和封堵膜。 布置与第一开口部分分离的第二开口部分（200），同时垂直地穿过模具膜和牺牲膜。 为了通过消除由第二开口部暴露的牺牲膜来露出保护膜，设置有凹部区域。 通过消除由凹部暴露的保护膜来露出封堵膜。
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公开(公告)号：KR1020100095263A
公开(公告)日：2010-08-30
申请号：KR1020090014449
申请日：2009-02-20
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247 , H01L29/792
CPC classification number: H01L27/11568 , H01L21/28282 , H01L27/11565 , H01L21/31051 , H01L21/76224
Abstract: PURPOSE: A nonvolatile memory device and a forming method thereof are provided to improve the reliability of a nonvolatile memory device by preventing a charge trap layer trapped on a first region from being moved to a second region. CONSTITUTION: A device isolation pattern(120) defines an active region(110) on a semiconductor substrate and is extended in a first direction. A charge trap layer(140) covers the active region and a device isolation pattern. A word line(160) is extended in a second direction cross the active region of the charge trap layer.
Abstract translation: 目的：提供一种非易失性存储器件及其形成方法，用于通过防止捕获在第一区域上的电荷陷阱层移动到第二区域来提高非易失性存储器件的可靠性。 构成：器件隔离图案（120）在半导体衬底上限定有源区（110）并沿第一方向延伸。 电荷陷阱层（140）覆盖有源区域和器件隔离图案。 字线（160）在与电荷陷阱层的有源区域交叉的第二方向上延伸。
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Patent Agency Ranking
公开(公告)号：KR100897602B1
公开(公告)日：2009-05-14
申请号：KR1020070016304
申请日：2007-02-16
Applicant: 삼성전자주식회사
CPC classification number: G11C29/48 , G11C29/1201 , G11C2029/2602
Abstract: 다수의 메모리부들을 포함하는 반도체 장치 및 상기 반도체 장치를 테스트하는 방법이 개시된다. 상기 반도체 장치는 각각이 다수의 입력 라인들을 포함하는 다수의 메모리부들, 테스트 인에이블 신호에 응답하여 다수의 테스트 신호들 중 대응하는 테스트 신호를 상기 다수의 메모리부들 각각에 포함된 상기 다수의 입력 라인들 중 대응되는 입력 라인으로 제공하는 입력부 및 상기 테스트 인에이블 신호에 응답하여 상기 테스트 장치로부터 Z(Z는 자연수)비트의 데이터를 수신하고 수신된 Z비트의 데이터를 상기 다수의 메모리부들로 분배하여 제공하는 데이터 입출력부를 구비한다. 상기 데이터 입출력부는 상기 다수의 메모리부들 각각으로부터 출력된 K(K≤(Z/M)인 자연수, M은 상기 다수의 메모리부들의 수) 비트의 데이터를 상기 다수의 메모리부들에 포함된 데이터 입출력 라인들을 통하여 출력한다.
반도체 장치.-
27.发明授权경사진 측벽을 갖는 활성 필라를 구비하는 비휘발성 메모리트랜지스터, 이를 구비하는 비휘발성 메모리 어레이 및상기 비휘발성 메모리 트랜지스터의 제조방법 有权非易失性存储器晶体管，包括具有斜面的活动支柱，具有晶体管的非易失性存储器阵列，以及制造晶体管的方法
公开(公告)号：KR100855992B1
公开(公告)日：2008-09-02
申请号：KR1020070032517
申请日：2007-04-02
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115
CPC classification number: H01L21/28282 , H01L21/28132 , H01L27/115 , H01L27/11568 , H01L29/1037 , H01L29/42332 , H01L29/42348 , H01L29/66787 , H01L29/7887 , H01L29/7923 , H01L29/7926 , H01L27/2463
Abstract: A non-volatile memory transistor including an active pillar having a sloped sidewall, a non-volatile memory array having the same, and a method for fabricating the same are provided to reduce power consumption by improving program efficiency. An active pillar(P) is protruded from a semiconductor substrate(10). The active pillar includes a sloped sidewall formed continuously from a surface of the semiconductor substrate. A gate electrode is formed to surround the sloped sidewall of the active pillar. An electric charge storage layer(23) is inserted between the active pillar and the gate electrode. A drain region(10d) is formed in an inside of an upper region of the active pillar. A source region(10s) is formed in the inside of the semiconductor substrate adjacent to a lower region of the active pillar.
Abstract translation: 提供了包括具有倾斜侧壁的有源支柱，具有其的非易失性存储器阵列及其制造方法的非易失性存储器晶体管，以通过提高程序效率来降低功耗。 活性柱（P）从半导体衬底（10）突出。 活性柱包括从半导体衬底的表面连续形成的倾斜侧壁。 栅电极形成为围绕有源支柱的倾斜侧壁。 电荷存储层（23）插入有源柱和栅电极之间。 漏极区域（10d）形成在有源支柱的上部区域的内部。 源极区域（10s）形成在与活性柱的下部区域相邻的半导体衬底的内部。
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公开(公告)号：KR100837397B1
公开(公告)日：2008-06-17
申请号：KR1020060001389
申请日：2006-01-05
Applicant: 삼성전자주식회사
IPC: G01N27/407 , G01N27/12 , B82B1/00
CPC classification number: G01N33/0054 , B82Y15/00 , G01N33/005 , Y02A50/246 , Y10S977/92
Abstract: 탄소나노튜브를 이용한 개스 센서 및 그 측정방법에 관해 개시한다. 개시된 탄소나노튜브를 이용한 개스 센서는 기판 상의 제1 및 제2전극을 연결하는 탄소나노튜브와, 상기 탄소나노튜브 상방에 설치된 광원과, 상기 제1 및 제2전극 사이의 전류를 측정하는 전류계를 구비한다. 이 개스센서를 사용하면, 다수의 미지의 개스 중 검출된 개스의 종류 및 농도를 함께 측정할 수 있다.
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公开(公告)号：KR1020080034685A
公开(公告)日：2008-04-22
申请号：KR1020060100947
申请日：2006-10-17
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/792 , H01L29/66833 , H01L29/7926 , H01L21/28282 , H01L21/31144
Abstract: An NVM(non-volatile memory) device is provided to improve electron injection efficiency by making the injection direction of electrons passing through the bottom surface of a charge trap layer have the transfer direction of electrons. A semiconductor substrate(104) includes a bottom part(104c) and a vertical part vertically protruding from the bottom part. The vertical part includes first and second vertical parts(104a,104b). A first vertical part is positioned in the upper part of the semiconductor substrate with respect to a boundary step. The second vertical part is positioned under the first vertical part, greater in width than the first vertical part and protruding to the outside of the first vertical part. A charge trap layer(134) is positioned outside the first vertical part and on the boundary step. A control gate electrode(150) is positioned on the bottom part and outside the second vertical part and the charge trap layer. A first insulation layer(124) can be interposed between the semiconductor substrate and the charge trap layer. A second insulation layer(144) can be interposed between the semiconductor substrate and the control gate electrode.
Abstract translation: 提供NVM（非易失性存储器）器件以通过使通过电荷陷阱层的底表面的电子的注入方向具有电子的传输方向来提高电子注入效率。 半导体衬底（104）包括底部（104c）和从底部垂直突出的垂直部分。 垂直部分包括第一和第二垂直部分（104a，104b）。 相对于边界步骤，第一垂直部分位于半导体衬底的上部。 第二垂直部分位于第一垂直部分下方，宽度大于第一垂直部分并且突出到第一垂直部分的外侧。 电荷捕获层（134）位于第一垂直部分的外侧和边界台阶上。 控制栅电极（150）位于第二垂直部分和电荷陷阱层的底部和外部。 第一绝缘层（124）可以插入在半导体衬底和电荷陷阱层之间。 可以在半导体衬底和控制栅电极之间插入第二绝缘层（144）。
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公开(公告)号：KR1020060053335A
公开(公告)日：2006-05-22
申请号：KR1020040093005
申请日：2004-11-15
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L21/31155 , B82Y10/00 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/7881 , H01L29/66825
Abstract: 이온주입을 이용한 비휘발성 메모리 소자 제조 방법 및 이에 따른 소자를 제시한다. 본 발명에 따르면, 반도체 기판 상에 유전층을 형성하고, 유전층 내에 실리콘(Si) 또는 저매니움(Ge)을 이온주입하여 전하포획자리로 사용될 이온주입층을 형성한다. 이후에, 어닐링(annealing) 과정을 수행할 수 있다. 유전층 상에 트랜지스터 형성 과정을 계속 수행할 수 있다.
비휘발성 메모리, 컨트롤 게이트, SONOS, 나노결정질체, 메모리 윈도우
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