公开(公告)号：KR1020040034172A

公开(公告)日：2004-04-28

申请号：KR1020020064255

申请日：2002-10-21

Applicant: 삼성전자주식회사

Inventor： 최재형 ,  유차영 ,  임한진 ,  김완돈 ,  정숙진 ,  이광희

IPC: H01L27/108

Abstract: PURPOSE: A method for manufacturing a semiconductor memory device is provided to be capable of improving the dielectric characteristic and depositing speed of a tantalum oxide layer and reducing leakage current. CONSTITUTION: A lower electrode(130) is formed on a semiconductor substrate. A stabilizing process is performed on the surface of the resultant structure. At this time, the lower electrode has oxygen atoms. A dielectric layer(140) is deposited on the resultant structure under inert gas atmosphere. At this time, the oxygen atoms are used for dissolving deposition source. A purging process is performed at a chamber, wherein the chamber is used for forming the dielectric layer. An upper electrode(150) is formed on the dielectric layer. Preferably, the lower electrode is made of ruthenium and platinum.

Abstract translation: 目的：提供一种制造半导体存储器件的方法，其能够改善钽氧化物层的介电特性和沉积速度并减少漏电流。 构成：在半导体衬底上形成下电极（130）。 在所得结构的表面上进行稳定化处理。 此时，下电极具有氧原子。 在惰性气体气氛下，在所得结构上沉积电介质层（140）。 此时，氧原子用于溶解沉积源。 在室中进行清洗过程，其中室用于形成电介质层。 在电介质层上形成上电极（150）。 优选地，下电极由钌和铂制成。

公开(公告)号：KR1020040020172A

公开(公告)日：2004-03-09

申请号：KR1020020051631

申请日：2002-08-29

Applicant: 삼성전자주식회사

Inventor： 이광희 ,  김완돈 ,  정숙진 ,  유차영 ,  최재형

IPC: H01L27/108

Abstract: PURPOSE: A semiconductor memory device and a method for manufacturing the same are provided to prevent the surface oxidation of a contact plug by forming an oxygen blocking layer in a lower electrode. CONSTITUTION: A contact plug(100) is formed on a semiconductor substrate. A lower electrode(140) is connected to the contact plug. A dielectric film(150) is formed on the lower electrode. An upper electrode(160) is formed on the dielectric film. At the time, the lower electrode(140) is provided with the first thin film(110), an oxygen blocking layer(120) and the second thin film(130). The oxygen blocking layer(120) is made of TaO.

Abstract translation: 目的：提供半导体存储器件及其制造方法，以通过在下电极中形成氧阻挡层来防止接触插塞的表面氧化。 构成：在半导体衬底上形成接触插塞（100）。 下电极（140）连接到接触插塞。 电介质膜（150）形成在下电极上。 在电介质膜上形成上电极（160）。 此时，下电极140具有第一薄膜110，氧阻挡层120和第二薄膜130。 氧阻挡层（120）由TaO制成。

公开(公告)号：KR1020030092872A

公开(公告)日：2003-12-06

申请号：KR1020020030710

申请日：2002-05-31

Applicant: 삼성전자주식회사

Inventor： 최재형 ,  유차영 ,  김완돈 ,  정숙진

IPC: H01L27/108

CPC classification number: H01L21/02183 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/55

Abstract: PURPOSE: A method for fabricating a dielectric layer of a capacitor is provided to improve capacitance and minimize leakage current inside the dielectric layer by improving the characteristic of the dielectric layer. CONSTITUTION: The capacitor(140) is composed of a lower electrode(110), the dielectric layer and an upper electrode(130). The first dielectric layer is deposited on the lower electrode. The first dielectric layer is crystallized. The second dielectric layer is epitaxially grown on the first dielectric layer to include the crystallinity of the first dielectric layer. The first and second dielectric layers are formed at the same temperature.

Abstract translation: 目的：提供一种用于制造电容器的电介质层的方法，以通过改善电介质层的特性来改善电容并最小化电介质层内部的漏电流。 构成：电容器（140）由下电极（110），电介质层和上电极（130）构成。 第一介电层沉积在下电极上。 第一介电层结晶。 在第一电介质层上外延生长第二电介质层以包括第一电介质层的结晶度。 第一和第二电介质层在相同的温度下形成。

公开(公告)号：KR102253595B1

公开(公告)日：2021-05-20

申请号：KR1020150001126

申请日：2015-01-06

Applicant: 삼성전자주식회사

Inventor： 오세훈 ,  박성율 ,  조진무 ,  최윤정 ,  박규희 ,  조윤정 ,  김윤수 ,  최재형

IPC: H01L49/02

Abstract: 반도체소자의제조방법은, 기판상에차례로적층된하부전극, 유전막, 및상부전극을포함하는캐패시터를형성하는것을포함한다. 상기상부전극을형성하는것은상기유전막상에제1 금속질화막을형성하는것, 및상기제1 금속질화막상에제2 금속질화막을형성하는것을포함한다. 상기제1 금속질화막은상기유전막과상기제2 금속질화막사이에개재되고, 상기제1 금속질화막은상기제2 금속질화막보다낮은온도에서형성된다.

公开(公告)号：KR102037868B1

公开(公告)日：2019-11-26

申请号：KR1020130023460

申请日：2013-03-05

Applicant: 삼성전자주식회사

Inventor： 박기연 ,  최재형 ,  블라디미르우라자에브 ,  정진하

IPC: H01L21/8242 ,  H01L27/108

公开(公告)号：KR101547313B1

公开(公告)日：2015-09-07

申请号：KR1020080117490

申请日：2008-11-25

Applicant: 삼성전자주식회사

Inventor： 임재순 ,  조규호 ,  최재형 ,  김윤수

IPC: H01L21/316

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513

Abstract: 유전막을갖는반도체소자를제공한다. 이소자는기판및 기판상에배치되고, 도핑원자들로도핑된하프늄산화막을포함한다. 도핑원자의이온크기는하프늄원자의이온크기보다크고, 도핑된하프늄산화막은정방정계단위격자들을포함한다.

公开(公告)号：KR1020110072331A

公开(公告)日：2011-06-29

申请号：KR1020090129209

申请日：2009-12-22

Applicant: 삼성전자주식회사

Inventor： 임재순 ,  김윤수 ,  최재형 ,  강상열 ,  정숙진

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L28/40 ,  C01G23/047 ,  C01G25/02 ,  C01P2002/72 ,  C01P2004/03 ,  C01P2006/40

Abstract: PURPOSE: A semiconductor device, a manufacturing method thereof, a semiconductor module including the same, an electronic circuit board, and an electronic system are provided to improve productivity by forming a semiconductor device with a capacitor including titanium oxide of rutile. CONSTITUTION: A lower vanadium dioxide layer(150) of rutile is formed on a bottom electrode. A titanium oxide layer(160) of rutile is formed on the lower vanadium dioxide layer. A top electrode(180) is formed on the titanium oxide layer. The bottom electrode includes vanadium. An upper vanadium dioxide layer of rutile is formed between the titanium oxide layer and the top electrode.

Abstract translation: 目的：提供一种半导体器件及其制造方法，包括该半导体器件的半导体模块，电子电路板和电子系统，以通过形成具有金红石氧化钛的电容器的半导体器件来提高生产率。 构成：在底部电极上形成金红石的较低二氧化钒层（150）。 在下层二氧化钒层上形成金红石的氧化钛层（160）。 顶部电极（180）形成在氧化钛层上。 底部电极包括钒。 在氧化钛层和顶部电极之间形成金红石的上层二氧化二钒层。

公开(公告)号：KR1020110021444A

公开(公告)日：2011-03-04

申请号：KR1020090079243

申请日：2009-08-26

Applicant: 삼성전자주식회사

Inventor： 손병근 ,  김한수 ,  안영수 ,  김민구 ,  김진호 ,  최재형 ,  최석헌

IPC: H01L27/115

CPC classification number: H01L27/11575 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L27/0688 ,  H01L21/76897 ,  H01L27/2463 ,  H01L2924/00

Abstract: PURPOSE: A 3d semiconductor memory apparatus and a manufacturing method thereof are provided to obtain the forming margin of a contact plugs or wirings directly connected to the contact extensions by arranging the contact extensions and the even conductive patterns on the different contact areas. CONSTITUTION: A substrate(10) comprises a cell array region(CAR) and contact areas(CR1, CR2). An extrusion oxide(11) is arranged on the contact area of the substrate. A plurality of conductive patterns(GL1~GL6) is deposited with an interval on the substrate. The conductive pattern comprises a wire portion(IC) which is parallel to the substrate and a contact extension part(CT) being tilted to the substrate.

Abstract translation: 目的：提供3d半导体存储装置及其制造方法，以通过将接触延伸部和偶数导电图案布置在不同的接触区域上来获得直接连接到接触延伸部的接触插塞或布线的成形边缘。 构成：衬底（10）包括电池阵列区（CAR）和接触区（CR1，CR2）。 挤出氧化物（11）设置在基板的接触区域上。 多个导电图案（GL1〜GL6）在衬底上以间隔沉积。 导电图案包括平行于基板的导线部分（IC）和向基板倾斜的接触延伸部分（CT）。

公开(公告)号：KR1020110008398A

公开(公告)日：2011-01-27

申请号：KR1020090065739

申请日：2009-07-20

Applicant: 삼성전자주식회사

Inventor： 최재형 ,  김윤수 ,  김중현 ,  김완돈 ,  임재순 ,  강상열

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L23/5223 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53261 ,  H01L28/56 ,  H01L28/91 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A layer structure, a capacitor including the layer structure and a method of manufacturing the same are provided to improve the interference characteristics between a conductive film and a dielectric film by forming the conductive film and the dielectric film. CONSTITUTION: A conductive film(110) is comprised of a metal-nitride including vanadium(V), niobium(Nb) or alloy of them. A dielectric layer(120) is formed on the conductive film while is comprise of a high-k dielectric material. A metal-nitride has a cubic crystalline structure or a hexagonal crystalline structure. Electric charge is stored inside the dielectric layer between electrodes facing with each other.

Abstract translation: 目的：提供层结构，包括层结构的电容器及其制造方法，以通过形成导电膜和电介质膜来改善导电膜和电介质膜之间的干涉特性。 构成：导电膜（110）由包括钒（V），铌（Nb）或它们的合金的金属氮化物组成。 介电层（120）形成在导电膜上，同时包含高k电介质材料。 金属氮化物具有立方晶体结构或六方晶系结构。 在电极彼此面对的电介质层之间存储电荷。

公开(公告)号：KR1020100006899A

公开(公告)日：2010-01-22

申请号：KR1020080067220

申请日：2008-07-10

Applicant: 삼성전자주식회사

Inventor： 임한진 ,  박재영 ,  김영진 ,  남석우 ,  김봉현 ,  윤경렬 ,  최재형 ,  김범종

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31641

Abstract: PURPOSE: A method for manufacturing a stack capacitor of a semiconductor device is provided to improve film quality of a dielectric film by suppressing the degradation like a surface oxidation of a bottom electrode or removing surface impurities of the bottom electrode through a preprocess. CONSTITUTION: A bottom electrode is formed on a semiconductor substrate(50). A preprocess is performed for degradation control of the bottom electrode. A dielectric film is formed on the bottom electrode(70). A top electrode is formed on the dielectric film(90). The preprocess and the formation of the dielectric film are performed in one equipment. The dielectric film formation process includes the preprocess. In the preprocess, the first source gas and the oxidizing agent for forming the dielectric film are injected into a chamber. One equipment uses an ALD(Atomic Layer Deposition) method.

Abstract translation: 目的：提供一种用于制造半导体器件的堆叠电容器的方法，以通过抑制诸如底电极的表面氧化的劣化或通过预处理去除底部电极的表面杂质来改善电介质膜的膜质量。 构成：在半导体衬底（50）上形成底部电极。 对底部电极的劣化控制进行预处理。 在底部电极（70）上形成电介质膜。 在电介质膜（90）上形成顶部电极。 电介质膜的预处理和形成在一个设备中进行。 介电膜形成工艺包括预处理。 在预处理中，将用于形成电介质膜的第一源气体和氧化剂注入室中。 一种设备使用ALD（原子层沉积）方法。