公开(公告)号：EP0907956B1

公开(公告)日：2000-05-31

申请号：EP97917123.8

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

公开(公告)号：EP0819308B1

公开(公告)日：1999-06-09

申请号：EP95943963.9

申请日：1995-12-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  FANG, Hao

IPC: G11C16/06

CPC classification number: G11C16/3477 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3486 ,  G11C2216/16 ,  G11C2216/18

Abstract: There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.

公开(公告)号：EP1386323A1

公开(公告)日：2004-02-04

申请号：EP02709575.1

申请日：2002-02-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FASTOW, Richard M. ,  GUO, Xin ,  HADDAD, Sameer

IPC: G11C16/34

CPC classification number: G11C16/3409 ,  G11C16/3404

Abstract: A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design are disclosed. The threshold voltage is compacted by erasing (602) a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying (604) at least one fast-erase memory cell; selectively soft-programming (606) the memory cells; and erasing (608) subsequent to selectively soft-programming.

公开(公告)号：EP1356505A1

公开(公告)日：2003-10-29

申请号：EP01957475.5

申请日：2001-08-06

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  HE, Yue-Song ,  THURGATE, Timothy ,  CHANG, Chi ,  WONG, Ngaching

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/66833

Abstract: One aspect of the present invention relates to a method of making a flash memory cell (32), involving providing a substrate (30) having a flash memory cell (32) thereon; forming a self-aligned source mask (48) over the substrate, the self aligned source mask (48) having openings (50) corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings (50) in the self-aligned source mask (48) corresponding to source lines (52); removing the self-aligned source mask (48) from the substrate (30); forming a MDD mask (54) over the substrate (30), the MDD mask (54) covering the source lines (52) and having openings (56) corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region (58) in the substrate (30) adjacent the flash memory cell (32).

公开(公告)号：EP1330840A1

公开(公告)日：2003-07-30

申请号：EP01959586.7

申请日：2001-08-06

Applicant: Advanced Micro Devices Inc.

Inventor： HE, Yue-Song ,  HADDAD, Sameer ,  THURGATE, Timothy ,  CHANG, Chi

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/66833

Abstract: One aspect of the present invention relates to a method of making a flash memory cell (32) involving the steps of providing a substrate (30) having a flash memory cell (32) thereon; forming a self-aligned source mask (48) over the substrate (30), the self aligned source mask (48) having openings (50) corresponding to source lines; implanting a source dopant of a first type (52) in the substrate (30) through the openings (50) in the self-aligned source mask (48) corresponding to source lines; removing the self-aligned source mask (48) from the substrate (30); cleaning the substrate (30); and implanting a medium dosage drain implant of a second type to form a source region (54) and a drain region (56) in the substrate (30) adjacent the flash memory cell (32).

公开(公告)号：EP0763258B1

公开(公告)日：2000-07-12

申请号：EP95936270.8

申请日：1995-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FANG, Hao ,  HADDAD, Sameer ,  CHANG, Chi

IPC: H01L27/02 ,  H01L27/115 ,  G11C5/00

CPC classification number: H01L27/0251 ,  H01L27/115

Abstract: An improved non-volatile memory device (10) is provided, in which the threshold voltage variations (Vts) and transconductance degradation are significantly reduced. The NVM (10) includes protection structure (200) for limiting the process induced damage incurred during the manufacturing process. The protection structure (200) is utilized to provide reliable and stable dielectrical characteristics for the NVM device (10). The protection structure (200) is easy to implement and will not affect the conventional NVM (10) performance.

公开(公告)号：EP0763258A2

公开(公告)日：1997-03-19

申请号：EP95936270.0

申请日：1995-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FANG, Hao ,  HADDAD, Sameer ,  CHANG, Chi

IPC: H01L27

CPC classification number: H01L27/0251 ,  H01L27/115

Abstract: An improved non-volatile memory device (10) is provided, in which the threshold voltage variations (Vts) and transconductance degradation are significantly reduced. The NVM (10) includes protection structure (200) for limiting the process induced damage incurred during the manufacturing process. The protection structure (200) is utilized to provide reliable and stable dielectrical characteristics for the NVM device (10). The protection structure (200) is easy to implement and will not affect the conventional NVM (10) performance.

公开(公告)号：EP1709682A1

公开(公告)日：2006-10-11

申请号：EP04814984.3

申请日：2004-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

IPC: H01L21/8246 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/792 ,  H01L29/10

CPC classification number: H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is patterned and a pocket implant (630) is performed at an angle to establish pocket implants (620) within the substrate (602). A bitline implant (634) is then performed to establish buried bitlines (640) within the substrate (602). The patterned resist is then removed and the remainder of the charge trapping dielectric layer (608) is formed. A wordline material (660) is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines (662) that overlie the bitlines (640). The pocket implants (620) serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

公开(公告)号：EP1395992A2

公开(公告)日：2004-03-10

申请号：EP02713624.1

申请日：2002-02-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WANG, Zhigang ,  FASTOW, Richard ,  HADDAD, Sameer ,  PARK, Sheung-Hee ,  CHANG, Chi

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404

Abstract: A source resistor or a positive voltage is couples to the source and a negative bias voltage is applied at the substance or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected. In a system and method for performing an APDE (Automatic Program Disturb after Erase) process, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A bit line APDE (Automatic program Disturb after Erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A control gate APDE (Automatic Program Disturb after Erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. Alternatively, the source is coupled to the control gate for each flash memory cell in a self-biasing configuration such that the control gate APDE voltage is not applied to the respective control gate of each flash memory cell of the selected column of flash memory cells.

公开(公告)号：EP1338032A2

公开(公告)日：2003-08-27

申请号：EP01990808.6

申请日：2001-10-30

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HE, Yue-Song ,  HADDAD, Sameer ,  FASTOW, Richard, M. ,  CHANG, Chi ,  WANG, Zhigang ,  PARK, Sheung-Hee

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

Abstract: For fabricating a flash memory cell on a semiconductor substrate, a channel dopant is implanted into the semiconductor substrate. The concentration of the channel dopang in the semiconductor substrate from the implantation process is less than about 4X1013/Cm2. A source line mask is formed over the substrate, and the source link mask has an opening to expose a source line of the semiconductor substrate. A source line dopant of a first conductivity type is implanted into the exposed source line of the semiconductor substrate. The source line mask is then removed from the semiconductor substrate. A drain mask is formed over the semiconductor substrate, and the drain mask has an opening to expose a drain region of the semiconductor substrate. A drain dopant of a second conductivity type is implanted into the exposed drain region of the semiconductor substrate. A channel region of the semiconductor substrate is disposed between the source line and the drain region. The first conductivity type of the source line dopant is opposite to the second conductivity type of the drain dopang. In addition, a conductivity type of the channel dopant is same as the first conductivity type of the source line dopant. The source line dopant that diffuses from the source line into the channel region is used to alter a threshold voltage of the flash memory cell and/or to reduce short channel effects of the flash memory cell such that a lower concentration of the channel dopant is implanted or such that the implantation of the channel dopant is even eliminated, for improved reliability and performance of the flash memory cell.