公开(公告)号：JP2006203908A

公开(公告)日：2006-08-03

申请号：JP2006013254

申请日：2006-01-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： SHUMARAYEV SERGEY Y ,  PATEL RAKESH H ,  WONG WILSON ,  HOANG TIM T

IPC: H03L7/087 ,  G06F1/06 ,  H03L7/08 ,  H03L7/081 ,  H04L7/033

CPC classification number: H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a technology for generating a restoring clock signal using a multi-mode clock data recovery (CDR) circuit meeting requirements of flexible ranged operating frequency F and continuous identical codes CID. SOLUTION: In first mode, a controlled oscillator provides the restoring clock signal, and in second mode, a phase interpolator provides the restoring clock signal. The multi-mode CDR circuit operates in the first mode when (CID/F) is less than a time tolerance, or operates in the second mode when the (CID/F) is greater than the time tolerance. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种使用满足柔性范围工作频率F和连续相同代码CID的要求的多模式时钟数据恢复（CDR）电路来产生恢复时钟信号的技术。 解决方案：在第一模式中，受控振荡器提供恢复时钟信号，而在第二模式中，相位内插器提供恢复时钟信号。 当（CID / F）小于时间容限时，多模式CDR电路在第一模式下工作，或者当（CID / F）大于时间容差时，多模式CDR电路在第一模式下工作。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE602006011974D1

公开(公告)日：2010-03-18

申请号：DE602006011974

申请日：2006-03-20

Applicant: ALTERA CORP

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  PATEL RAKESH H

IPC: H03K19/177

Abstract: A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

公开(公告)号：DE60210387T2

公开(公告)日：2007-01-04

申请号：DE60210387

申请日：2002-09-11

Applicant: ALTERA CORP

Inventor： ANDRASIC STJEPAN WILLIAM ,  PATEL RAKESH H ,  LEE CHONG H

IPC: H03K5/13 ,  H03H11/26 ,  H03K3/03 ,  H03K3/353 ,  H03K3/354 ,  H03L7/099 ,  H03L7/10

Abstract: A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator ("VCO") includes a plurality of such delay cells connected in a closed loop series. Phase locked loop ("PLL") circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

公开(公告)号：DE60210387D1

公开(公告)日：2006-05-18

申请号：DE60210387

申请日：2002-09-11

Applicant: ALTERA CORP

Inventor： ANDRASIC STJEPAN WILLIAM ,  PATEL RAKESH H ,  LEE CHONG H

IPC: H03K5/13 ,  H03H11/26 ,  H03K3/03 ,  H03K3/353 ,  H03K3/354 ,  H03L7/099 ,  H03L7/10

Abstract: A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator ("VCO") includes a plurality of such delay cells connected in a closed loop series. Phase locked loop ("PLL") circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

公开(公告)号：GB2351824B

公开(公告)日：2004-03-31

申请号：GB0016223

申请日：2000-06-30

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

IPC: G11C5/02 ,  H03K19/177

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

公开(公告)号：GB2349998B

公开(公告)日：2001-02-28

申请号：GB0020337

申请日：1997-05-28

Applicant: ALTERA CORP

Inventor： PATEL RAKESH H ,  TURNER JOHN E ,  LAM JOHN D ,  WONG WILSON

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0185

公开(公告)号：GB2349999B

公开(公告)日：2001-01-31

申请号：GB0020344

申请日：1997-05-28

Applicant: ALTERA CORP

Inventor： PATEL RAKESH H ,  TURNER JOHN E ,  LAM JOHN D ,  WONG WILSON

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0185

公开(公告)号：GB2349999A

公开(公告)日：2000-11-15

申请号：GB0020344

申请日：1997-05-28

Applicant: ALTERA CORP

Inventor： PATEL RAKESH H ,  TURNER JOHN E ,  LAM JOHN D ,  WONG WILSON

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0185

Abstract: Reverse conduction through the PMOS pull-up device MP3 is prevented by providing a 5 volt gate potential when MP3 is off. Conduction through the substrate of MP3 is prevented by connecting the substrate to the 5 volt supply instead of to the source of MP3. The output driver may be used in a programmable logic circuit with a logic core operating at 3 volts. The 5 volt supply may be generated on-chip by a voltage pump.

公开(公告)号：GB2286703B

公开(公告)日：1997-11-19

申请号：GB9501878

申请日：1995-01-31

Applicant: ALTERA CORP

Inventor： PATEL RAKESH H ,  WONG MYRON W

IPC: G06F11/20 ,  H03K19/003 ,  H03K19/173 ,  H03K19/177

Abstract: A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into use in place of the defective circuitry by programming appropriate portions of the circuitry of the programmable logic device. The programmable logic device is arranged in rows and columns of programmable logic containing logic array blocks, which a user selectively configures by loading programming data into vertical and horizontal programming blocks. Programming blocks are used to program the logic array blocks and various associated logic circuitry. When the redundant circuitry is switched into place, the programming data is redirected to the appropriate programming blocks, so that the device functions identically, regardless of whether or not the redundant circuitry is used.