公开(公告)号：GB2556260A

公开(公告)日：2018-05-23

申请号：GB201801219

申请日：2016-12-15

Applicant: IBM

Inventor： RAJASEKHAR VENIGALLA ,  SEONG-DONG KIM ,  BRUCE DORIS ,  BRENT A ANDERSON

IPC: H01L29/786

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess (170) in a substrate (100); epitaxially growing a first drain (400) from the first bottom surface (190) of the first recess (170); epitaxially growing a second drain (600) from the second bottom surface (195) of a second recess (175) formed in the substrate (100); growing a channel material (700) epitaxially on the first drain (400) and the second drain (600); forming troughs (740) in the channel material (700) to form one or more fin channels (750) on the first drain (400) and one or more fin channels (750) on the second drain (600), wherein the troughs (740) over the first drain (400) extend to the surface of the first drain (400), and the troughs (740) over the second drain (600) extend to the surface of the second drain (600); forming a gate structure (1030) on each of the one or more fin channels (750); and growing sources (1520, 1540) on each of the fin channels (750) associated with the first drain (400) and the second drain (500).

公开(公告)号：GB2556224A

公开(公告)日：2018-05-23

申请号：GB201720310

申请日：2016-05-06

Applicant: IBM

Inventor： SIVANANDA KANAKASABAPATHY ,  FEE LI LIE ,  GAURI KARVE ,  SOON-CHEON SEO ,  STUART SIEG ,  HONG HE ,  DERRICK LIU ,  BRUCE DORIS

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion (14P) having an end wall (15W) and extending upward from a substrate (10). A gate structure (16) straddles a portion of the semiconductor fin portion (14P). A first set of gate spacers (24P/50P) is located on opposing sidewall surfaces of the gate structure (16L/16R); and a second set of gate spacers (32P) is located on sidewalls of the first set of gate spacers (24P/50P). One gate spacer of the second set of spacers (32P) has a lower portion that directly contacts the end wall (15W) of the semiconductor fin portion (14P).

公开(公告)号：GB2550740A

公开(公告)日：2017-11-29

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer(20) disposed on a substrate(10), a silicon germanium layer(30) disposed on the dielectric layer(20), and a strained semiconductor material layer(40) disposed directly on the silicon germanium layer(30), forming a plurality of fins(43, 45) on the SSOI structure, forming a gate structure(50) over a portion of at least one fin in a nFET region, forming a gate structure(60) over a portion of at least one fin in a pFET region, removing the gate structure(60) over the portion of the at least one fin in the pFET region, removing the silicon germanium layer(30) exposed by the removing, and forming a new gate structure(90) over the portion of the at least one fin in the pFET region, such that the new gate structure(90) surrounds the portion on all four sides.